[PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs

[Joel Stanley]

Hi Stephen,

On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel at jms.id.au> wrote:
>
> On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew at aj.id.au> wrote:
> >
> > RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> > single gate for each MAC.
> >
> > Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
>
> Reviewed-by: Joel Stanley <joel at jms.id.au>

I noticed this one hasn't been applied to clk-next.

Cheers,

Joel