[PATCH 4/4] mtd: spi-nor: aspeed: introduce optimized settings for fast reads
joel at jms.id.au
Mon Jul 23 22:16:01 AEST 2018
On 22 June 2018 at 21:44, Cédric Le Goater <clg at kaod.org> wrote:
> Better settings for fast reads are looked for by implementing a SPI
> timing calibration sequence described in the Aspeed SoC specification
> document. The code is based on the OpenPOWER pflash tool and a similar
> sequence using DMAs can be found in the SDK U-Boot.
> The SPI calibration performs a loop on different SPI clock rates
> (dividers of the AHB clock rates) and on different input delay cycles
> for each SPI clock rates. The successive read results are compared to
> a golden buffer, read at low speed, to select the safest and fastest
> read settings for the chip.
> The "spi-max-frequency" property is used to cap the optimize read
> algorithm on some devices or controllers for which we want a "really"
> safe setting, on the FMC controller chips for instance.
> It can also be deactivated at boot time with a kernel parameter
> 'optimize_read', but that was never used on the field.
> Signed-off-by: Cédric Le Goater <clg at kaod.org>
Reviewed-by: Joel Stanley <joel at jms.id.au>
I have also been running these applied to a 4.17 base on ast2400 and
ast2500 systems for the past few months. This week I gave them a spin
on top of linux-next too.
They have looked good so far, so I would encourage the series to me
merged for 4.19 so we can reduce the number of out of tree we use in
For the series:
Tested-by: Joel Stanley <joel at jms.id.au>
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