[PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part

[Thierry Reding]

On Fri, Jul 12, 2013 at 03:31:23PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote:
[...]
> >  	/* set the number of lines as 4 */
> > -	readl_rc(pp, dbi_base + PCIE_PORT_LINK_CONTROL, &val);
> > +	dw_pcie_readl_rc(pp, dbi_base + PCIE_PORT_LINK_CONTROL, &val);
> >  	val &= ~PORT_LINK_MODE_MASK;
> >  	val |= PORT_LINK_MODE_4_LANES;
> > -	writel_rc(pp, val, dbi_base + PCIE_PORT_LINK_CONTROL);
> > +	dw_pcie_writel_rc(pp, val, dbi_base + PCIE_PORT_LINK_CONTROL);
> 
> I guess here we need to make this configurable. In Jacinto6 this can be either
> single lane or double lane. Maybe we should have a dt property to specify the
> number of lanes?

On Tegra we use nvidia,num-lanes to specify the lane count for each
port. Perhaps standardizing on a generic num-lanes property would make
sense? Cc'ing devicetree-discuss mailing list, maybe somebody can
provide some guidance.

Thierry
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