Pin control mappings for DT

[Linus Walleij]

On Tue, Nov 29, 2011 at 6:55 PM, Stephen Warren <swarren at nvidia.com> wrote:
> Linus Walleij wrote at Tuesday, November 29, 2011 12:42 AM:

>> 1) Per-driver info, includes the pin controller base, its pins, their
>>  (optional) names and their specific presets like bias etc.
>
> I'm still planning on putting this all into the driver source code; I
> don't really see any advantage of putting this almost static data into
> DT just to parse it back out into the same tables that could be written
> straight into the driver anyway. (only almost static rather than static
> since we'll need new tables for each SoC)

I think OMAP already have a few different SoCs using the same
pinmux HW block, so for them it makes more sense.

Maybe when you have your Tegra 7 chips using the same
controller as Tegra { 3, 4, 5, 6 } with yet another pin list
it will make sense :-)

Besides - doing it one way does not exclude the other.

If the tables gets large I will have Torvalds on my tail for
putting nonsensical lists into the kernel that'd better been
kept outside it.

Yours,
Linus Walleij