standard property to convey device dma address width?

[Kumar Gala]

On Aug 16, 2010, at 3:17 PM, Mitch Bradley wrote:

> Kumar Gala wrote:
>> Do we or should we have a standard property to convey that address width a device is capable of?
>>  
> 
> What is the context?  When Open Firmware was first developed, the only bus with partial addresses was ISA.  The ISA bus binding has a "dma" property that describes some of the legacy DMA characteristics, but address width isn't one of them, for reasons that I don't remember.
> 
> I thought at the time (perhaps wishfully) that partial addresses would not be consideration for future buses, because
> 
> a) The transition to large-scale integration had already made logic gates nearly "free", so there was no motivation to skimp on address register bits.
> 
> b) Although packages were - and still are - pin-limited, partial address bus connections were not feasible because of uneven bus loading problems.
> 
> c) Address and data buses were usually multiplexed onto the same pins, further reducing the motivation for partial addresses.
> 
> Obviously, since you are asking the question, there is some case where address width could be variable.  I'd be interested to learn the details.
> 
> If I had to describe a partial address, I'd consider a property name like "dma-address-mask", whose value is a bitmap of implemented bits, corresponding to the bits in a unit address for the parent bus.  Low-order bits might be zero if the DMA addressing hardware had alignment restrictions.

As I said to Stuart.  On the Freescale SOCs we have different device blocks w/varying dma address capabilities.  Some are limited to 32-bits some are capable of 36-bits on the same SOC.

- k