[Cbe-oss-dev] [RFC/PATCH] adding support for direct MBX interrupt on Axon based platform.

[Benjamin Herrenschmidt]

On Fri, 2007-05-18 at 16:09 +0200, Arnd Bergmann wrote:
> Hi JC,
> 
> Thanks for sending out this patch, I know people have been waiting
> for it. I never understood how it's wired and how it should be
> in the device-tree, this makes things much clearer.
> 
> I think the mpic device node actually should be changed to point to
> the c3po as its parent, but that would mean that you can't boot
> an old linux kernel on a new device tree, because the code to
> handle c3po is missing there.

No real need for that I think.

> Is the priority the only way you can distinguish mpic interrupts
> from non-mpic ones?

If that is the case, a better approach is to have a different cascade
handler. That is, mailbox interrupts have basically the same
"interrupts" as MPIC "upstream". 

Then, we have, in the cell platform code, a cascade handler registered
on that interrupt that checks the mailbox sources and cascades
eventually to the MPIC.

However, I think we -can- use a different class instead. If you look at
Axon INTx_INFO registers, the class is programable. Thus we could use
class 1 for mailbox interrupts and the problem is solved provided that
the mailbox uses a different INTx_INFO than the MPIC upstream, which I
think is the case (INT2_INFO afaik).

So what if you set that interrupts's class to 0 or 1 in Axon instead ?
That would give you a different irq number than you can then just
request_irq() off the iic PIC.

Ben.