[Cbe-oss-dev] [patch 3/5] cell: updated driver for DDR2 memory on AXON

[Arnd Bergmann]

On Thursday 21 June 2007, Christophe Lamoureux wrote:
> 
> > +     BUG_ON(!bank);
> > +
> > +     if (irq == bank->irq_correctable) {
> > +             dev_err(&device->dev, "Correctable memory error occured\n");
> > +             bank->ecc_counter++;
> It's minor but shouldn't the interrupt be acknowledged on the axon Memory Controler device here ? 
> The goal is to reset the level of the interrupt line between the Memory Controler and the MPIC, so 
> being able to catch the next correctable ecc errors ( this driver has registered the irq on trigger rising  
> and the axon MC specs looks to say the interrupt for the MC is level only )  

Yes, I guess you are right, thanks for the hint. Maxim, can you comment on this?

	Arnd <><