[Cbe-oss-dev] [PATCH] 64K support for Kexec

[Segher Boessenkool]

>> static inline void __tlbie(unsigned long va, unsigned int psize)
>> {
>>         unsigned int penc;
>>
>>         /* clear top 16 bits, non SLS segment */
>>         va &= ~(0xffffULL << 48);
>>
>> why does this routine clear the top 16 bits?
>>
>> SLS - single level store.  all segments are non-sls?
>
> I should remove the comment about non SLS segment. The reason about
> masking the top 16 bits is simply because the doc says to do so.
>
>> From PPC AS 2.01, doc of tlbie:
>
> "The contents of (RB)0:15 must be 0x0000."

But AS isn't relevant for Linux.  The PowerPC arch 2.03
shows bits 0..15 as part of the VPN field.

> Do you think that isn't correct for newer processors ?

It shouldn't matter much, those bits will be zero anyway
as nothing implements that big an address space AFAIK.
Some might get close though.


Segher