[Cbe-oss-dev] [PATCH] 64K support for Kexec

[Benjamin Herrenschmidt]

On Sat, 2007-04-07 at 00:16 -0300, Luke Browning wrote:
> static inline void __tlbie(unsigned long va, unsigned int psize)
> {
>         unsigned int penc;
> 
>         /* clear top 16 bits, non SLS segment */
>         va &= ~(0xffffULL << 48);
> 
> why does this routine clear the top 16 bits?  
> 
> SLS - single level store.  all segments are non-sls?  

I should remove the comment about non SLS segment. The reason about
masking the top 16 bits is simply because the doc says to do so.

>From PPC AS 2.01, doc of tlbie:

"The contents of (RB)0:15 must be 0x0000."

Do you think that isn't correct for newer processors ? Right now, I
don't have a more recent PPC_AS at hand. I have a copy of the RFC2054
but I'm not sure it's the latest one as it contains some confusing
things regarding tlbie, I'll have to double check on monday. However, in
the cell PPE BookIV, I see:

"This implementation supports bits [22:(63 – p)], of the RB source
register for tlbie and tlbiel"

Thus I don't think bits 0...15 matter. Anton, can you check wether I
should change tlbie/tlbiel in hash_native_64.c a bit more in that area ?
I think the magic bit 56 thingy is not useful for us (we don't do MPSS).

Luke, if you think you have a problem still in that area, you can try
changing the invalidation selector (IS bits) that we don't set (set to
0) and use 11 instead which would invalidate regardless of the page
size, though that's cell specific afaik. (just a good test to do).

Ben.