[Cbe-oss-dev] [PATCH] fix reboot fail on kexec for CBE

[Segher Boessenkool]

> It looks like you have some "magic" SPRs to do the job, care to provide
> a bit more details about the approach ?

It's just the software TLB load mechanism; details
about that are in the BE Handbook, the CBEA ref,
the CBE registers doc.

+       for (i = 0; i < 256; i++) {
+               ti = 0x10 * i;
+               for (j = 0; j < 4; j++) {
+                       ts = 1 << j;
+                       tmp = ti | ts;
+                       mtspr(947, tmp);
+                       mtspr(948, 0);
+               }
+       }

SPR 947 is PPE_TLB_Index; the low four bits are a bitmask
that selects which TLB sets to write, the eight bits above
that select which TLB index.  SPR 948 is PPE_TLB_VPN; the
low bit selects whether the TLB entry is valid.  This
register should be written last.

These invalidations aren't broadcast to other CPUs.  This
insn sequence doesn't clear the ERATs as far as I can see;
only tlbie(l) does that.  Maybe that's a good thing here;
is this code running with translation off?

Anyway, this code can be written more simple as

+       for (i = 0; i < 256; i++) {
+               mtspr(947, 0x10 * i + 0x0f);
+               mtspr(948, 0);
+       }

since it is perfectly allowed to write to multiple sets
at once (just not very useful in most cases).


Segher