[PATCH v2 1/1] ARM:dts:aspeed: Initial device tree for AMD Onyx Platform

Andrew Lunn andrew at lunn.ch
Sat Mar 2 09:36:41 AEDT 2024


> +&mdio0 {
> +	status = "okay";
> +	ethphy0: ethernet-phy at 0 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <0>;
> +	};
> +};
> +
> +&mac3 {
> +	status = "okay";
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_rgmii4_default>;
> +};

That looks odd. Where are the RGMII delays coming from? Normally its
"rgmii-id", which asks the PHY to insert the delays.

	Andrew


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