[Skiboot] [PATCH] cpu: Fix HID SPR icache flushing and attn change sequence

[Reza Arbab]

On Sat, May 28, 2022 at 12:21:48AM +1000, Nicholas Piggin wrote:
>Changing the HID attn enable bit on POWER9 and POWER10 requires the
>icache to be flushed *after* ATTN is changed. It is not clear that it
>may be done at the same time, so move it to after the attn bit change.
>
>Flushing the icache with HID requires a 0->1 edge and the bit does not
>reset back to 0, so first write 1 then 0 ready for the next flush.

Applied to master.

-- 
Reza Arbab