[Skiboot] [PATCH 1/1] AWAN simulator support for P10
Ryan Grimm
grimm at linux.ibm.com
Thu Sep 9 02:57:59 AEST 2021
This patch enables Skiboot to initialize and Linux to boot to user space
on the AWAN core and chip models.
We need the distinction between core and chip models because the core
models do not have an XSCOM unit, CHIPTOD, nor RNG. The chip
model does have them and they work.
So, add a device_type property to the awan node to distinguish core from
chip. Sample DTS are provided for the core and chip models in
external/awan.
Just like Mambo, we need to return in slw_init before trying to
initialize SLW. Without an XSCOM unit in the device tree for the core
model, the SLW code path eventually fails an assert due to lack of
chips.
This commit defines a QUIRK_AWAN where previously Mambo used
QUIRK_MAMBO_CALLOUTS so now Mambo and AWAN core both work.
Also, fix up chip quirks so the core model and chip model boot and
initialize the appropriate units.
Disable sreset and power management in a couple spots because the chip
model does not support stop with EC=1 and enter_p9_pm_state spins in the
branch-to-self after stop.
Provide an external/awan/README.md with a high-level view of booting in
the environment.
Signed-off-by: Ryan Grimm <grimm at linux.ibm.com>
---
core/chip.c | 17 +++-
core/cpu.c | 5 +-
core/init.c | 2 +-
external/awan/README.md | 34 +++++++
external/awan/p10_chip_2ex_smt4.dts | 135 ++++++++++++++++++++++++++++
external/awan/p10_core_1ex_smt4.dts | 69 ++++++++++++++
hw/slw.c | 7 +-
include/chip.h | 1 +
8 files changed, 262 insertions(+), 8 deletions(-)
create mode 100644 external/awan/README.md
create mode 100644 external/awan/p10_chip_2ex_smt4.dts
create mode 100644 external/awan/p10_core_1ex_smt4.dts
diff --git a/core/chip.c b/core/chip.c
index 2d95b2e05..6fc5d423d 100644
--- a/core/chip.c
+++ b/core/chip.c
@@ -166,11 +166,20 @@ void init_chips(void)
prlog(PR_NOTICE, "CHIP: Detected Simics simulator\n");
}
/* Detect Awan emulator */
- if (dt_find_by_path(dt_root, "/awan")) {
- proc_chip_quirks |= QUIRK_NO_CHIPTOD | QUIRK_NO_F000F
- | QUIRK_NO_PBA | QUIRK_NO_OCC_IRQ | QUIRK_SLOW_SIM;
+ xn = dt_find_by_path(dt_root, "/awan");
+ if (xn) {
+ const char *model_type;
+ proc_chip_quirks |= QUIRK_AWAN | QUIRK_SLOW_SIM | QUIRK_NO_PBA
+ | QUIRK_NO_OCC_IRQ;
tb_hz = 512000;
- prlog(PR_NOTICE, "CHIP: Detected Awan emulator\n");
+
+ model_type = dt_prop_get_def(xn, "device_type", (void *)"core");
+ if (strcmp(model_type, "core") == 0) {
+ proc_chip_quirks |= QUIRK_NO_RNG | QUIRK_NO_CHIPTOD
+ | QUIRK_NO_F000F;
+ }
+ prlog(PR_NOTICE, "CHIP: Detected Awan emulator %s model\n",
+ model_type);
}
/* Detect Qemu */
if (dt_node_is_compatible(dt_root, "qemu,powernv") ||
diff --git a/core/cpu.c b/core/cpu.c
index f58aeb27a..bf76ac7ed 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -633,6 +633,9 @@ static void cpu_pm_disable(void)
void cpu_set_sreset_enable(bool enabled)
{
+ if (proc_chip_quirks & QUIRK_AWAN)
+ return;
+
if (sreset_enabled == enabled)
return;
@@ -684,7 +687,7 @@ void cpu_set_ipi_enable(bool enabled)
sync();
if (!enabled)
cpu_pm_disable();
- else
+ else if (!chip_quirk(QUIRK_AWAN))
pm_enabled = true;
}
}
diff --git a/core/init.c b/core/init.c
index a8bac28a8..4f8e3f59a 100644
--- a/core/init.c
+++ b/core/init.c
@@ -999,7 +999,7 @@ static void mask_pc_system_xstop(void)
if (proc_gen != proc_gen_p10)
return;
- if (chip_quirk(QUIRK_MAMBO_CALLOUTS))
+ if (chip_quirk(QUIRK_MAMBO_CALLOUTS) || chip_quirk(QUIRK_AWAN))
return;
/*
diff --git a/external/awan/README.md b/external/awan/README.md
new file mode 100644
index 000000000..d625b5a4f
--- /dev/null
+++ b/external/awan/README.md
@@ -0,0 +1,34 @@
+# Running skiboot and Linux in AWAN
+
+AWAN is a hardware accelerator composed of programmable gate arrays that can
+emulate a POWER logic core. The AWAN environment can be used to run hardware
+procedures or test binaries on the logic, before hardware is available or when
+hardware is scarce.
+
+The AWAN environment is slow compared to Mambo and QEMU. Each timebase tick is
+equivalent to 8 simclocks, and simclock is slow. For example, on the core
+model we get through Skiboot in about 6 million simclock cycles and that takes
+approximately 1 minute wall-clock time to complete.
+
+# Getting started
+
+To run in AWAN, you need a an initial checkpoint, a loader, and a method to
+read memory.
+
+The high-level sequence for running in AWAN is:
+
+1. Load an initial checkpoint provided by the person that built the model
+
+2. Load a stripped vmlinux at 0
+
+3. Load an initramfs at 0x28200000
+
+4. Load skiboot.lid at 0x30000000
+
+5. Load a small piece of start code at 0x100 that tells skiboot where to find
+ the device tree blob
+
+6. Load a compiled device tree blob at 0x1f00000
+
+7. Run "simclock 5000000" and check the console buffer for the Skiboot log
+ by reading memory at 784MB.
diff --git a/external/awan/p10_chip_2ex_smt4.dts b/external/awan/p10_chip_2ex_smt4.dts
new file mode 100644
index 000000000..61d474de5
--- /dev/null
+++ b/external/awan/p10_chip_2ex_smt4.dts
@@ -0,0 +1,135 @@
+/dts-v1/;
+
+/ {
+ compatible = "ibm,powernv";
+ model = "BML";
+ #size-cells = <0x2>;
+ #address-cells = <0x2>;
+
+ reserved-names = "ibm,fake-nvram";
+ reserved-ranges = <0x0 0x28100000 0x0 0x100000>;
+
+ chosen {
+ kernel-base-address = <0x00 0x00>;
+ linux,initrd-start = <0x28200000>;
+ linux,initrd-end = <0x28200800>;
+ };
+
+ awan {
+ device_type = "chip";
+ };
+
+ memory at 0 {
+ reg = <0x0 0x0 0x0 0x80000000>;
+ ibm,chip-id = <0x0>;
+ device_type = "memory";
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ PowerPC,POWER10 at 18 {
+ name = "PowerPC,POWER10";
+ device_type = "cpu";
+ status = "okay";
+ ibm,chip-id = <0x00>;
+ ibm,pir = <0x18>;
+ reg = <0x18>;
+ timebase-frequency = <512000000>;
+ clock-frequency = <3250000000>;
+ ibm,segment-page-sizes = <0x0c 0x00 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x08 0x18 0x100 0x1 0x18 0x00 0x22 0x120 0x1 0x22 0x03>;
+ ibm,processor-segment-sizes = <0x0000001c 0x28 0xffffffff 0xffffffff>;
+ ibm,vmx = <0x2>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
+ i-cache-line-size = <0x80>;
+ d-cache-line-size = <0x80>;
+ ibm,slb-size = <0x20>;
+ ibm,ppc-interrupt-server#s = <0x18 0x19 0x1a 0x1b>;
+ ibm,pa-features = <0x4000f63f 0xc7c080d0 0x80000000 0x00000000 0x00008000 0x80008000 0x00008000 0x80008000 0x00008000 0x80000000 0x80008000 0x80008000 0x80008000 0x80008000 0x80008000 0x80000000 0x80000000 0x00000000>;
+ ibm,processor-radix-AP-encodings = <0x0000000c 0xa0000010 0x20000015 0x4000001e>;
+ ibm,dfp = <0x2>;
+ };
+
+ PowerPC,POWER10 at 1c {
+ name = "PowerPC,POWER10";
+ device_type = "cpu";
+ status = "okay";
+ ibm,chip-id = <0x00>;
+ ibm,pir = <0x1c>;
+ reg = <0x1c>;
+ timebase-frequency = <512000000>;
+ clock-frequency = <3250000000>;
+ ibm,segment-page-sizes = <0x0c 0x00 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x08 0x18 0x100 0x1 0x18 0x00 0x22 0x120 0x1 0x22 0x03>;
+ ibm,processor-segment-sizes = <0x0000001c 0x28 0xffffffff 0xffffffff>;
+ ibm,vmx = <0x2>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
+ i-cache-line-size = <0x80>;
+ d-cache-line-size = <0x80>;
+ ibm,slb-size = <0x20>;
+ ibm,ppc-interrupt-server#s = <0x1c 0x1d 0x1e 0x1f>;
+ ibm,pa-features = <0x4000f63f 0xc7c080d0 0x80000000 0x00000000 0x00008000 0x80008000 0x00008000 0x80008000 0x00008000 0x80000000 0x80008000 0x80008000 0x80008000 0x80008000 0x80008000 0x80000000 0x80000000 0x00000000>;
+ ibm,processor-radix-AP-encodings = <0x0000000c 0xa0000010 0x20000015 0x4000001e>;
+ ibm,dfp = <0x2>;
+ };
+ };
+
+ xscom at e03fc00000000 {
+ compatible = "ibm,xscom", "ibm,power10-xscom";
+ ibm,chip-id = <0x0>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0xe03fc 0x00000000 0x8 0x0>;
+
+ ibm,primary-topology-index = <0x0>;
+
+ chiptod at 40000 {
+ primary;
+ reg = <0x40000 0x34>;
+ compatible = "ibm,power-chiptod", "ibm,power10-chiptod";
+ };
+
+ xive at 2010800 {
+ compatible = "ibm,power10-xive-x";
+ reg = < 0x2010800 0x400 >;
+ force-assign-bars;
+ };
+
+ psihb at 3011d00 {
+ compatible = "ibm,power10-psihb-x", ibm,psihb-x";
+ #size-cells = < 0x01 >;
+ #address-cells = < 0x02 >;
+ reg = < 0x3011d00 0x100 >;
+ };
+
+ nx at 2010000 {
+ reg = <0x2010000 0x4000>;
+ compatible = "ibm,power9-nx";
+ };
+
+ vas at 2011400 {
+ reg = <0x2011400 0x300>;
+ compatible = "ibm,power9-vas-x", "ibm,power10-vas-x";
+ ibm,vas-id = < 0x0 >;
+ };
+
+ nmmu at 2010c40 {
+ reg = <0x2010c40 0x20>;
+ compatible = "ibm,power9-nest-mmu";
+ };
+
+ nmmu at 3010c40 {
+ reg = <0x3010c40 0x20>;
+ compatible = "ibm,power9-nest-mmu";
+ };
+ };
+
+ ibm,opal {
+ power-mgt {
+ ibm,enabled-stop-levels = <0x0>;
+ };
+ };
+
+};
diff --git a/external/awan/p10_core_1ex_smt4.dts b/external/awan/p10_core_1ex_smt4.dts
new file mode 100644
index 000000000..1794ae9e9
--- /dev/null
+++ b/external/awan/p10_core_1ex_smt4.dts
@@ -0,0 +1,69 @@
+/dts-v1/;
+
+/ {
+ compatible = "ibm,powernv";
+ model = "BML";
+ #size-cells = <0x2>;
+ #address-cells = <0x2>;
+
+ reserved-names = "ibm,fake-nvram";
+ reserved-ranges = <0x0 0x28100000 0x0 0x100000>;
+
+ chosen {
+ kernel-base-address = <0x00 0x00>;
+ linux,initrd-start = <0x28200000>;
+ linux,initrd-end = <0x28200800>;
+ linux,stdout-path = "/chosen/stdout";
+ };
+
+ awan {
+ device_type = "core";
+ };
+
+ memory at 0 {
+ reg = <0x0 0x0 0x0 0x80000000>;
+ ibm,chip-id = <0x0>;
+ device_type = "memory";
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ PowerPC,POWER10 at 0 {
+ name = "PowerPC,POWER10";
+ device_type = "cpu";
+ status = "okay";
+ ibm,chip-id = <0x0>;
+ ibm,pir = <0x0>;
+ reg = <0x0>;
+ timebase-frequency = <512000000>;
+ clock-frequency = <3400000000>;
+ ibm,segment-page-sizes = <0x0c 0x00 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x08 0x18 0x100 0x1 0x18 0x00 0x22 0x120 0x1 0x22 0x03>;
+ ibm,processor-segment-sizes = <0x0000001c 0x28 0xffffffff 0xffffffff>;
+ ibm,vmx = <0x2>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
+ i-cache-line-size = <0x80>;
+ d-cache-line-size = <0x80>;
+ ibm,slb-size = <0x20>;
+ ibm,ppc-interrupt-server#s = <0x0 0x1 0x2 0x3>;
+ ibm,pa-features = <0x4000f63f 0xc7c080d0 0x80000000 0x00000000 0x00008000 0x80008000 0x00008000 0x80008000 0x00008000 0x80000000 0x80008000 0x80008000 0x80008000 0x80008000 0x80008000 0x80000000 0x80000000 0x00000000>;
+ ibm,processor-radix-AP-encodings = <0x0000000c 0xa0000010 0x20000015 0x4000001e>;
+ ibm,dfp = <0x2>;
+ };
+ };
+
+ pmem {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ pmem at 80000000 {
+ reg = <0x0 0x80000000 0x0 0x8000000>;
+ ibm,chip-id = <0x00>;
+ compatible = "pmem-region";
+ volatile;
+ };
+ };
+};
diff --git a/hw/slw.c b/hw/slw.c
index 56ba05b0a..239b7213e 100644
--- a/hw/slw.c
+++ b/hw/slw.c
@@ -1695,11 +1695,14 @@ void slw_init(void)
{
struct proc_chip *chip;
- if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) {
- wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT;
+ wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT;
+ if (chip_quirk(QUIRK_AWAN))
+ return;
+ if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) {
add_cpu_idle_state_properties();
return;
}
+
if (proc_gen == proc_gen_p8) {
for_each_chip(chip) {
slw_init_chip_p8(chip);
diff --git a/include/chip.h b/include/chip.h
index bbfc65e3a..cfa5ce351 100644
--- a/include/chip.h
+++ b/include/chip.h
@@ -186,6 +186,7 @@ enum proc_chip_quirks {
QUIRK_NO_DIRECT_CTL = 0x00000080,
QUIRK_NO_RNG = 0x00000100,
QUIRK_QEMU = 0x00000200,
+ QUIRK_AWAN = 0x00000400,
};
extern enum proc_chip_quirks proc_chip_quirks;
--
2.25.1
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