[Skiboot] [PATCH v2 1/2] external/mambo: Updates for POWER10 configuration for DD2.0

[Nicholas Piggin]

Update PVR and mambo f000f bits:
- Set POWER10 to DD2.0

Update SIM_CTRL and SIM_CTRL1 bits:
- Set the LPAR-per-core mode bit. This is required for SMT KVM to work.
- Set ARC0/ARC1 bits which enable atomic RC update interrupts (not
  hardware updates), which matches implementation.
- Enable DEXCR, HAIL, ROP, BHRB disable, block BHRB writes in PR=0,
  and RFC02628 on POWER10.

Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
---

Since v1 "external/mambo: Updates for POWER9 and POWER10 configuration"
this was split into 2 patches (POWER9 and POWER10), with some bits fixed
up and a workaround for SIM_CTRL added.

I couldn't get POWER9 lpar-per-thread small core mode to quite work, but
at least disabling hardware atomic RC updates can be done.

Thanks,
Nick

 external/mambo/skiboot.tcl | 18 +++++++++++++++---
 hw/xscom.c                 |  2 +-
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/external/mambo/skiboot.tcl b/external/mambo/skiboot.tcl
index 91617b75c..8038d2a91 100644
--- a/external/mambo/skiboot.tcl
+++ b/external/mambo/skiboot.tcl
@@ -144,9 +144,11 @@ if { $default_config == "P9" } {
 }
 
 if { $default_config == "P10" } {
-    # PVR configured for POWER10 DD1.0
-    myconf config processor/initial/PVR 0x800100
-    myconf config processor/initial/SIM_CTRL1 0xc228100400000000
+    # PVR configured for POWER10 DD2.0, big-core, LPAR-per-thread
+    # Small-core has bit 0x1000 set.
+    myconf config processor/initial/PVR 0x800200
+    myconf config processor/initial/SIM_CTRL  0x0c1dd60000000000
+    myconf config processor/initial/SIM_CTRL1 0xc0400c0400040a40
 
     if { $mconf(numa) } {
         myconf config memory_region_id_shift 44
@@ -164,6 +166,16 @@ if { [info exists env(SKIBOOT_SIMCONF)] } {
 
 define machine myconf mysim
 
+# Some mambo does not expose SIM_CTRL as a config option. Also set the SPRs
+# after machine is defined.
+if { $default_config == "P10" } {
+    for { set c 0 } { $c < $mconf(cpus) } { incr c } {
+        for { set t 0 } { $t < $mconf(threads) } { incr t } {
+	    mysim mcm 0 cpu $c thread $t set spr ctrl 0x0c1dd60000000000
+        }
+    }
+}
+
 #
 # Include various utilities
 #
diff --git a/hw/xscom.c b/hw/xscom.c
index 347457242..298fe0c90 100644
--- a/hw/xscom.c
+++ b/hw/xscom.c
@@ -826,7 +826,7 @@ int64_t xscom_read_cfam_chipid(uint32_t partid, uint32_t *chip_id)
 	 */
 	if (chip_quirk(QUIRK_NO_F000F)) {
 		if (proc_gen == proc_gen_p10)
-			val = 0x120DA04980000000UL; /* P10 DD1.0 */
+			val = 0x220DA04980000000UL; /* P10 DD2.0 */
 		else if (proc_gen == proc_gen_p9)
 			val = 0x203D104980000000UL; /* P9 Nimbus DD2.3 */
 		else
-- 
2.23.0