[Skiboot] [PATCH 3/8] cpu: add debug check in cpu_relax

[Cédric Le Goater]

Hello,

On 10/3/21 03:22, Nicholas Piggin wrote:
> If cpu_relax() is called when not at medium SMT priority, it will lose
> the prior priority and return at medium. Add a debug check to catch
> this, which would have flagged the previous bug.
> 
> Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
> ---
>   core/cpu.c          | 6 ++++++
>   include/processor.h | 1 +
>   2 files changed, 7 insertions(+)
> 
> diff --git a/core/cpu.c b/core/cpu.c
> index 5c10fc6e8..0f2da1524 100644
> --- a/core/cpu.c
> +++ b/core/cpu.c
> @@ -80,6 +80,12 @@ unsigned long __attrconst cpu_emergency_stack_top(unsigned int pir)
>   
>   void __nomcount cpu_relax(void)
>   {
> +	if ((mfspr(SPR_PPR32) >> 18) != 0x4) {


Why not use  SPR_PPR ? SPR_PPR32 is for the embedded world according
to ISA.

Thanks,

C.


> +		printf("cpu_relax called when not at medium SMT priority: "
> +			"PPR[PRI]=0x%lx\n", mfspr(SPR_PPR32) >> 18);
> +		backtrace();
> +	}
> +
>   	/* Relax a bit to give sibling threads some breathing space */
>   	smt_lowest();
>   	asm volatile("nop; nop; nop; nop;\n"
> diff --git a/include/processor.h b/include/processor.h
> index 973d7e77b..7a9c49994 100644
> --- a/include/processor.h
> +++ b/include/processor.h
> @@ -71,6 +71,7 @@
>   #define SPR_USRR1	0x1fb   /* RW: Ultravisor Save/Restore Register 1 */
>   #define SPR_SMFCTRL	0x1ff   /* RW: Secure Memory Facility Control */
>   #define SPR_PSSCR	0x357   /* RW: Stop status and control (ISA 3) */
> +#define SPR_PPR32	0x382
>   #define SPR_TSCR	0x399
>   #define SPR_HID0	0x3f0
>   #define SPR_HID1	0x3f1
>