[Skiboot] [PATCH 05/10] hw/slw: Move P8 bits behind CONFIG_P8
Nicholas Piggin
npiggin at gmail.com
Sat Jun 26 12:38:19 AEST 2021
This saves about 3kB from skiboot.lid.xz
Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
---
core/fast-reboot.c | 2 +
hw/slw.c | 136 +++++++++++++++++++++++--------------------
libpore/Makefile.inc | 8 ++-
3 files changed, 80 insertions(+), 66 deletions(-)
diff --git a/core/fast-reboot.c b/core/fast-reboot.c
index 03777543a..c7288e3d6 100644
--- a/core/fast-reboot.c
+++ b/core/fast-reboot.c
@@ -267,6 +267,7 @@ static void cleanup_cpu_state(void)
if (cpu_is_thread0(cpu)) {
/* XXX should reset the SLW SPR restore values*/
+#ifdef CONFIG_P8
if (proc_gen == proc_gen_p8) {
/* If somebody was in fast_sleep, we may have a
* workaround to undo
@@ -282,6 +283,7 @@ static void cleanup_cpu_state(void)
*/
cleanup_local_tlb();
}
+#endif
/* And we might have lost TB sync */
chiptod_wakeup_resync();
diff --git a/hw/slw.c b/hw/slw.c
index 2f78b0e6c..9428e155d 100644
--- a/hw/slw.c
+++ b/hw/slw.c
@@ -31,19 +31,20 @@
enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT;
bool has_deep_states = false;
-DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
- OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL,
- OPAL_NA);
-
DEFINE_LOG_ENTRY(OPAL_RC_SLW_SET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
OPAL_PLATFORM_FIRMWARE, OPAL_INFO,
OPAL_NA);
-DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
+DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
OPAL_PLATFORM_FIRMWARE, OPAL_INFO,
OPAL_NA);
-DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
+#ifdef CONFIG_P8
+DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
+ OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL,
+ OPAL_NA);
+
+DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
OPAL_PLATFORM_FIRMWARE, OPAL_INFO,
OPAL_NA);
@@ -97,39 +98,6 @@ static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c)
return true;
}
-static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c)
-{
- uint64_t tmp;
- int rc;
- uint32_t core = pir_to_core_id(c->pir);
-
- /* Clear special wakeup bits that could hold power mgt */
- rc = xscom_write(chip->id,
- XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP),
- 0);
- if (rc) {
- log_simple_error(&e_info(OPAL_RC_SLW_SET),
- "SLW: Failed to write EC_PPM_SPECIAL_WKUP_HYP\n");
- return false;
- }
- /* Read back for debug */
- rc = xscom_read(chip->id,
- XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP),
- &tmp);
- if (tmp)
- prlog(PR_WARNING,
- "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n",
- core, tmp);
- rc = xscom_read(chip->id,
- XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR),
- &tmp);
- if (tmp)
- prlog(PR_WARNING,
- "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n",
- core, tmp);
- return true;
-}
-
static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c)
{
uint32_t core = pir_to_core_id(c->pir);
@@ -221,6 +189,40 @@ static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c)
return true;
}
+#endif
+
+static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c)
+{
+ uint64_t tmp;
+ int rc;
+ uint32_t core = pir_to_core_id(c->pir);
+
+ /* Clear special wakeup bits that could hold power mgt */
+ rc = xscom_write(chip->id,
+ XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP),
+ 0);
+ if (rc) {
+ log_simple_error(&e_info(OPAL_RC_SLW_SET),
+ "SLW: Failed to write EC_PPM_SPECIAL_WKUP_HYP\n");
+ return false;
+ }
+ /* Read back for debug */
+ rc = xscom_read(chip->id,
+ XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP),
+ &tmp);
+ if (tmp)
+ prlog(PR_WARNING,
+ "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n",
+ core, tmp);
+ rc = xscom_read(chip->id,
+ XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR),
+ &tmp);
+ if (tmp)
+ prlog(PR_WARNING,
+ "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n",
+ core, tmp);
+ return true;
+}
/* Define device-tree fields */
#define MAX_NAME_LEN 16
@@ -923,31 +925,6 @@ void add_cpu_idle_state_properties(void)
free(pm_ctrl_reg_mask_buf);
}
-static void slw_patch_regs(struct proc_chip *chip)
-{
- struct cpu_thread *c;
- void *image = (void *)chip->slw_base;
- int rc;
-
- for_each_available_cpu(c) {
- if (c->chip_id != chip->id)
- continue;
-
- /* Clear HRMOR */
- rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM,
- P8_SPR_HRMOR, 0,
- cpu_get_core_index(c),
- cpu_get_thread_index(c));
- if (rc) {
- log_simple_error(&e_info(OPAL_RC_SLW_REG),
- "SLW: Failed to set HRMOR for CPU %x\n",
- c->pir);
- }
-
- /* XXX Add HIDs etc... */
- }
-}
-
static void slw_init_chip_p9(struct proc_chip *chip)
{
struct cpu_thread *c;
@@ -975,6 +952,32 @@ static bool slw_image_check_p9(struct proc_chip *chip)
}
+#ifdef CONFIG_P8
+static void slw_patch_regs(struct proc_chip *chip)
+{
+ struct cpu_thread *c;
+ void *image = (void *)chip->slw_base;
+ int rc;
+
+ for_each_available_cpu(c) {
+ if (c->chip_id != chip->id)
+ continue;
+
+ /* Clear HRMOR */
+ rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM,
+ P8_SPR_HRMOR, 0,
+ cpu_get_core_index(c),
+ cpu_get_thread_index(c));
+ if (rc) {
+ log_simple_error(&e_info(OPAL_RC_SLW_REG),
+ "SLW: Failed to set HRMOR for CPU %x\n",
+ c->pir);
+ }
+
+ /* XXX Add HIDs etc... */
+ }
+}
+
static bool slw_image_check_p8(struct proc_chip *chip)
{
int64_t rc;
@@ -1124,6 +1127,7 @@ static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter)
}
opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2);
+#endif
int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
{
@@ -1159,6 +1163,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
rc = p9_stop_save_cpureg((void *)chip->homer_base,
sprn, val, cpu_pir);
+#ifdef CONFIG_P8
} else if (proc_gen == proc_gen_p8) {
int spr_is_supported = 0;
void *image;
@@ -1182,6 +1187,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
sprn, val,
cpu_get_core_index(c),
cpu_get_thread_index(c));
+#endif
} else {
log_simple_error(&e_info(OPAL_RC_SLW_REG),
"SLW: proc_gen not supported\n");
@@ -1213,6 +1219,7 @@ void slw_init(void)
return;
}
if (proc_gen == proc_gen_p8) {
+#ifdef CONFIG_P8
for_each_chip(chip) {
slw_init_chip_p8(chip);
if(slw_image_check_p8(chip))
@@ -1221,6 +1228,7 @@ void slw_init(void)
slw_late_init_p8(chip);
}
p8_sbe_init_timer();
+#endif
} else if (proc_gen == proc_gen_p9) {
for_each_chip(chip) {
slw_init_chip_p9(chip);
diff --git a/libpore/Makefile.inc b/libpore/Makefile.inc
index 1060a0492..701bb1004 100644
--- a/libpore/Makefile.inc
+++ b/libpore/Makefile.inc
@@ -1,5 +1,9 @@
-LIBPORE_SRCS = p8_pore_table_gen_api_fixed.C p9_stop_api.C p9_stop_util.C
-LIBPORE_SRCS += p8_pore_table_static_data.c sbe_xip_image.c pore_inline_assembler.c
+LIBPORE_SRCS = p9_stop_api.C p9_stop_util.C
+LIBPORE_SRCS += sbe_xip_image.c pore_inline_assembler.c
+ifeq ($(CONFIG_P8),1)
+LIBPORE_SRCS += p8_pore_table_gen_api_fixed.C p8_pore_table_static_data.c
+endif
+
LIBPORE_OBJS_1 = $(LIBPORE_SRCS:%.c=%.o)
LIBPORE_OBJS = $(LIBPORE_OBJS_1:%.C=%.o)
SUBDIRS += libpore
--
2.23.0
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