[Skiboot] [PATCH 24/61] NX: Set VAS RMA write BAR register on P10

[Vasant Hegde]

From: Haren Myneni <haren at linux.ibm.com>

For each NX instance, VAS RMA write BAR register should be set with
the corresponding VAS RMA BAR value.

Refer section: 5.30 VAS RMA write BAR (P10 NX work Book V1.01)

Signed-off-by: Haren Myneni <haren at linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant at linux.vnet.ibm.com>
---
 hw/nx-compress.c | 36 ++++++++++++++++++++++++++++++++++++
 hw/vas.c         | 18 ++++++++++++++++++
 include/nx.h     |  3 +++
 include/vas.h    |  1 +
 4 files changed, 58 insertions(+)

diff --git a/hw/nx-compress.c b/hw/nx-compress.c
index b2302866b..9b3c6717d 100644
--- a/hw/nx-compress.c
+++ b/hw/nx-compress.c
@@ -115,6 +115,30 @@ static int nx_cfg_umac_status_ctrl(u32 gcid, u64 xcfg)
 	return rc;
 }
 
+static int nx_cfg_vas_rma_bar(u32 gcid, u64 xcfg)
+{
+	int rc = 0;
+	u64 cfg;
+
+	cfg = vas_get_rma_bar(gcid);
+	/*
+	 * NOTE: Write the entire bar address to SCOM. VAS/NX will extract
+	 *	 the relevant (NX_P10_VAS_RMA_WRITE_BAR) bits. IOW, _don't_
+	 *	 just write the bit field like:
+	 *	 cfg = SETFIELD(NX_P10_VAS_RMA_WRITE_BAR, 0ULL, cfg);
+	 */
+	rc = xscom_write(gcid, xcfg, cfg);
+
+	if (rc)
+		prerror("NX%d: ERROR: VAS RMA WRITE BAR, %d\n", gcid, rc);
+	else
+		prlog(PR_DEBUG, "NX%d: VAS RMA WRITE BAR, 0x%016lx, "
+				"xcfg 0x%llx\n", gcid, (unsigned long)cfg,
+				xcfg);
+
+	return rc;
+}
+
 int nx_cfg_rx_fifo(struct dt_node *node, const char *compat,
 			const char *priority, u32 gcid, u32 pid, u32 tid,
 			u64 umac_bar, u64 umac_notify)
@@ -272,6 +296,10 @@ void nx_create_compress_node(struct dt_node *node)
 
 	prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base);
 
+	/*
+	 * ibm,power9-nx is compatible on P10. So using same
+	 * compatible string.
+	 */
 	if (dt_node_is_compatible(node, "ibm,power9-nx")) {
 		u64 cfg_mmio, cfg_txwc, cfg_uctrl, cfg_dma;
 
@@ -297,6 +325,14 @@ void nx_create_compress_node(struct dt_node *node)
 		if (rc)
 			return;
 
+		if (proc_gen > proc_gen_p9) {
+			u64 cfg_rma = pb_base + NX_P10_VAS_RMA_WRITE_BAR;
+
+			rc = nx_cfg_vas_rma_bar(gcid, cfg_rma);
+			if (rc)
+				return;
+		}
+
 		p9_nx_enable_842(node, gcid, pb_base);
 		p9_nx_enable_gzip(node, gcid, pb_base);
 	} else
diff --git a/hw/vas.c b/hw/vas.c
index 8617b8d59..6a7bd1c10 100644
--- a/hw/vas.c
+++ b/hw/vas.c
@@ -279,6 +279,24 @@ static void get_rma_bar(struct proc_chip *chip, uint64_t *val)
 	*val = v;
 }
 
+/* Interface for NX - make sure VAS is fully initialized first */
+__attrconst uint64_t vas_get_rma_bar(int chipid)
+{
+	struct proc_chip *chip;
+	uint64_t addr;
+
+	if (!vas_initialized)
+		return 0ULL;
+
+	chip = get_chip(chipid);
+	if (!chip)
+		return 0ULL;
+
+	get_rma_bar(chip, &addr);
+
+	return addr;
+}
+
 /*
  * Initialize RMA BAR on this chip to correspond to its node/chip id.
  * This will cause VAS to accept paste commands to targeted for this chip.
diff --git a/include/nx.h b/include/nx.h
index 5734e24a3..c42d165e9 100644
--- a/include/nx.h
+++ b/include/nx.h
@@ -141,6 +141,9 @@
 
 #define NX_P9_ERAT_STATUS_CTRL			NX_P9_SAT(0x3, 0x16)
 
+/* Introduced in P10, but P10 NX SCOM address is same as P9 */
+#define	NX_P10_VAS_RMA_WRITE_BAR		NX_P9_SAT(0x3, 0x19)
+
 /* NX Status Register */
 #define NX_P8_STATUS		NX_P8_SAT(0x1, 0x00)
 #define NX_P9_STATUS		NX_P9_SAT(0x1, 0x00) /* DMA Status register */
diff --git a/include/vas.h b/include/vas.h
index 369c3807a..1f59b1d9c 100644
--- a/include/vas.h
+++ b/include/vas.h
@@ -27,6 +27,7 @@ extern void vas_init(void);
 extern __attrconst bool vas_nx_enabled(void);
 extern __attrconst uint64_t vas_get_hvwc_mmio_bar(const int chipid);
 extern __attrconst uint64_t vas_get_wcbs_bar(int chipid);
+extern __attrconst uint64_t vas_get_rma_bar(int chipid);
 
 /*
  * HVWC and UWC BAR.
-- 
2.31.1