[Skiboot] [RFC PATCH] chiptod: properly zero TB SPR when cleaning up for invalid TB

Nicholas Piggin npiggin at gmail.com
Fri Dec 17 13:24:39 AEDT 2021

The existing sequence writes TBU twice and leaves TBL unchanged. This
may not really matter if it's being resynced from the chiptod soon, but
it's possible it could clear a parity error.

Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
I did not find the recovery recipe or reason to clear TBU twice in the
workbook. So it looks odd and the new sequence follows the ISA
requirement to zero the TB register, but maybe I overlook something. If
2x mfTBU is required then it should have a comment IMO.

 hw/chiptod.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/chiptod.c b/hw/chiptod.c
index 7c0a1ffc7..736bd03fa 100644
--- a/hw/chiptod.c
+++ b/hw/chiptod.c
@@ -1556,8 +1556,9 @@ void tfmr_cleanup_core_errors(uint64_t tfmr)
 	 * restored after the next rendez-vous
 	if (!(tfmr & SPR_TFMR_TB_VALID)) {
+		mtspr(SPR_TBWL, 0);
 		mtspr(SPR_TBWU, 0);
-		mtspr(SPR_TBWU, 0);
+		mtspr(SPR_TBWL, 0);

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