[Skiboot] [PATCH 1/3] xive/p10: Fix xive_special_cache_check when DEBUG=1

Vasant Hegde hegdevasant at linux.vnet.ibm.com
Thu Aug 19 21:40:50 AEST 2021

On 8/7/21 1:08 PM, Cédric Le Goater wrote:
> The special cache check done when skiboot is compiled with DEBUG is
> incompatible with Automatic Context Save and Restore.
> Random data is written in the NVP to check that cache updates are
> correct but this can lead to a checkstop raised by the XIVE interrupt
> controller. When the NVP Valid (0) bit, the hardware controlled H (7)
> bit, and the Checked Out bit (45) are all ones at the same time, the
> HW thinks that the NVP entry is checked out by a thread and does not
> allow the cache write to occur.
> Make sure that the valid bit is not set on the NVP.
> Signed-off-by: Cédric Le Goater <clg at kaod.org>

Thanks! Merged series to master as of cd12ea6d.


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