[Skiboot] [PATCH v2 00/59] P10 Enablement
Vasant Hegde
hegdevasant at linux.vnet.ibm.com
Wed Aug 4 17:20:38 AEST 2021
This series adds P10 support. This includes various features along with base
P10 support like xive2, phb5, P10 stop states, 2nd DAWR support, etc,. It also
adds support for rainier and denali platform support.
WARNING: skiboot LID size crossing 512K limit
With this patchset signed skiboot lid size (skiboot.lid.xz.stb) is crossing
512K (Its around 514K on my FC33 system with gcc v10.3.1). Current rainier
(P10 BMC system) has skiboot LID (PAYLOAD partition) size limit as 512K
(see [1]). We are working on increasing PAYLAOD partition size to 1MB.
Until its fixed build skiboot LID with CONFIG_FSP=0 option. This will
build LID without FSP component and LID size will be ~470K.
[1] https://github.ibm.com/open-power/pnor/blob/master-p10/p10Layouts/defaultPnorLayout_64.xml
Alistair Popple (2):
hw/phys-map/p10: Add P10 MMIO map
platforms: Add Rainier
Anju T Sudhakar (1):
hw/imc: Power10 support
Cédric Le Goater (19):
plat/qemu/p10: add a POWER10 platform
psi/p10: Activate P10 interrupts
xive/p10: Add a XIVE2 driver
psi/p10: Activate 64K ESB pages
psi/p10: Activate StoreEOI
xive/p10: Add option flags to the XIVE exploitation mode
hw/phb5: Add support for PQ offloading
hw/phb5: Add support for 'Address-Based Interrupt Trigger' mode
psi/p10: Introduce xive2_source_mask()
psi/p10: Mask all sources at init
xive/p10: Introduce new capability bits
xive/p10: Configure XIVE for fused cores
xive/p10: Add automatic Context Save and Restore support
xive/p10: Introduce a new OPAL_XIVE_IRQ_STORE_EOI2 flag
xive/p10: Activate split mode for PHB ESBs when PQ_disable is
available
xive/p10: Activate has_array when PQ_disable is available
xive/p10: Tune max_entries_in_modified when split_mode is on
xive/p10: Change alignment of the queue overflow pages
phb5: Activate StoreEOI for LSIs
Frederic Barrat (7):
hdata/iohub: Read PCI Gen5 equalization settings for P10
hw/phb5: Update PHB numbering to allow for virtual PHBs
phb5: Add register inits specific to Gen5
phb5: Workaround for PCI bug HW551382
phb4: Cleanup PEC config discovery in CAPI mode
phb4/5: Fix PHB link width detection to avoid useless retrainings
phb5: Fix PHB max link speed definition on P10
Haren Myneni (5):
hdat/spira: Define ibm,primary-topology-index property per chip
hdat/spira: Add ibm,power10-vas-x string to VAS compatible property
VAS: Define Remote Memory Access paste address on P10
VAS: Enable VAS on P10
NX: Set VAS RMA write BAR register on P10
Jordan Niethe (1):
hw/phb5: Add initial support
Klaus Heinrich Kiwi (1):
external/gard: Enable Power10
Michael Neuling (2):
p10: Workaround core recovery issue
phb5: Enable Gen5
Nicholas Piggin (4):
external/mambo: skiboot.tcl add POWER10 config
Initial POWER10 enablement
cpufeatures: Add POWER10 support
hw/chiptod: Add POWER10 support
Oliver O'Halloran (3):
hw/p8-i2c: Add POWER10 support
prd: Add base P10 support
hw/psi-p10: Configure interrupt offset before notify addr
Pratik Rajesh Sampat (1):
libpore: P10 stop-api support
Ravi Bangoria (1):
hdata: Add POWER10 support
Reza Arbab (1):
platforms/astbmc: Add ast2600
Ryan Grimm (2):
hw/nx: Enable p10 DARN
hw/chiptod: Retry the sync procedure on failure
Vaidyanathan Srinivasan (3):
Basic P10 stop state support
occ: Add POWER10 support
xive2: Add NCU_SPEC_BAR to stop engine for restore
Vasant Hegde (6):
external/xscom-utils: Add P10 chip info
external/opal-prd: Fix occ, homer node label search
hdata/P10: Fix xscom address and ibm,chip-id property
phys/P10: Use topology index to get phys mapping
platform: Add Denali platform support
hw/chiptod: Abort if core frequency is not set
asm/head.S | 55 +-
asm/misc.S | 4 +-
core/affinity.c | 2 +
core/chip.c | 44 +-
core/cpu.c | 32 +-
core/cpufeatures.c | 104 +-
core/direct-controls.c | 386 +-
core/fast-reboot.c | 4 +
core/hmi.c | 225 +-
core/init.c | 52 +-
core/mce.c | 129 +-
core/test/run-timer.c | 2 +-
.../opal-pci-set-phb-capi-mode-93.rst | 5 +-
doc/platforms-and-cpus.rst | 1 +
external/gard/gard.c | 15 +-
external/gard/gard.h | 1 +
external/gard/test/results/02-usage.err | 1 +
external/gard/units.c | 89 +
external/mambo/skiboot.tcl | 34 +-
external/opal-prd/opal-prd.c | 16 +-
external/xscom-utils/adu_scoms.py | 2 +
external/xscom-utils/getscom.c | 3 +
external/xscom-utils/sram.c | 2 +
hdata/cpu-common.c | 19 +-
hdata/fsp.c | 16 +-
hdata/hdata.h | 2 +
hdata/i2c.c | 5 +-
hdata/iohub.c | 81 +-
hdata/memory.c | 8 +-
hdata/spira.c | 147 +-
hdata/spira.h | 37 +-
hdata/test/hdata_to_dt.c | 14 +-
hw/Makefile.inc | 2 +-
hw/capp.c | 11 +-
hw/chiptod.c | 143 +-
hw/dts.c | 7 +-
hw/fsp/fsp-occ.c | 3 +-
hw/fsp/fsp-psi.c | 1 +
hw/fsp/fsp.c | 5 +
hw/homer.c | 16 +
hw/imc.c | 61 +-
hw/lpc.c | 7 +-
hw/nx-compress.c | 36 +
hw/nx.c | 29 +-
hw/occ-sensor.c | 4 +-
hw/occ.c | 172 +-
hw/p8-i2c.c | 29 +-
hw/phb4.c | 473 +-
hw/phys-map.c | 105 +-
hw/prd.c | 5 +
hw/psi.c | 115 +-
hw/slw.c | 218 +-
hw/test/phys-map-test.c | 25 +-
hw/vas.c | 121 +-
hw/xive.c | 6 +-
hw/xive2.c | 4665 +++++++++++++++++
hw/xscom.c | 25 +-
include/chip.h | 52 +
include/imc.h | 2 +
include/nx.h | 3 +
include/opal-api.h | 6 +-
include/p10_stop_api.H | 239 +
include/phb4-regs.h | 31 +-
include/phb4.h | 23 +-
include/phys-map.h | 13 +-
include/processor.h | 52 +-
include/psi.h | 13 +-
include/skiboot.h | 1 +
include/vas.h | 6 +-
include/xive.h | 36 +
include/xive2-regs.h | 581 ++
include/xscom-p10-regs.h | 56 +
include/xscom.h | 85 +
libpore/Makefile.inc | 2 +-
libpore/p10_cpu_reg_restore_instruction.H | 88 +
libpore/p10_hcd_header_defs.H | 152 +
libpore/p10_hcd_memmap_base.H | 463 ++
libpore/p10_hcd_memmap_homer.H | 94 +
libpore/p10_hcd_memmap_occ_sram.H | 174 +
libpore/p10_hcode_image_defines.H | 462 ++
libpore/p10_stop_api.C | 1816 +++++++
libpore/p10_stop_api.H | 238 +
libpore/p10_stop_data_struct.H | 162 +
libpore/p10_stop_util.C | 190 +
libpore/p10_stop_util.H | 123 +
platforms/astbmc/Makefile.inc | 3 +-
platforms/astbmc/astbmc.h | 2 +
platforms/astbmc/common.c | 19 +-
platforms/astbmc/rainier.c | 136 +
platforms/ibm-fsp/hostservices.c | 4 +
platforms/ibm-fsp/zz.c | 6 +
91 files changed, 12728 insertions(+), 426 deletions(-)
create mode 100644 hw/xive2.c
create mode 100644 include/p10_stop_api.H
create mode 100644 include/xive2-regs.h
create mode 100644 include/xscom-p10-regs.h
create mode 100644 libpore/p10_cpu_reg_restore_instruction.H
create mode 100644 libpore/p10_hcd_header_defs.H
create mode 100644 libpore/p10_hcd_memmap_base.H
create mode 100644 libpore/p10_hcd_memmap_homer.H
create mode 100644 libpore/p10_hcd_memmap_occ_sram.H
create mode 100644 libpore/p10_hcode_image_defines.H
create mode 100644 libpore/p10_stop_api.C
create mode 100644 libpore/p10_stop_api.H
create mode 100644 libpore/p10_stop_data_struct.H
create mode 100644 libpore/p10_stop_util.C
create mode 100644 libpore/p10_stop_util.H
create mode 100644 platforms/astbmc/rainier.c
--
2.31.1
More information about the Skiboot
mailing list