[Skiboot] [RFC PATCH v5 03/16] Disable protected execution facility

[Alexey Kardashevskiy]

On 28/02/2020 07:40, Ryan Grimm wrote:
> This patch disables Protected Execution Faciltiy (PEF).
> 
> This software procedure is needed for the lab because Cronus will be
> configured to bring the machine up with PEF on.  Hostboot has a similar
> procedure for running with PEF off.
> 
> Skiboot can run with PEF on but the kernel cannot; the kernel will take
> a machine check when trying to write a protected resource, such as the
> PTCR.
> 
> So, use this until we have an ultravisor, or if we want to use BML with
> Cronus without UV = 1.
> 
> Signed-off-by: Ryan Grimm <grimm at linux.ibm.com>
> ---
>  asm/misc.S          | 39 +++++++++++++++++++++++++++++++++++++++
>  include/processor.h |  3 +++
>  2 files changed, 42 insertions(+)
> 
> diff --git a/asm/misc.S b/asm/misc.S
> index f9dea492..9d2f3b6e 100644
> --- a/asm/misc.S
> +++ b/asm/misc.S
> @@ -277,3 +277,42 @@ start_uv:
>  	ld      %r0,16(%r1)
>  	mtlr    %r0
>  	blr
> +
> +/*
> + * Exit UV mode and disable Protected Execution Facility
> + * For each core, this should be run on all secondary threads first to bring
> + * them out of UV mode.  Then, it is called by the primary thread to disable
> + * PEF and bring it out of UV mode.  All threads will then be running in HV
> + * mode.  The only way to reenable UV mode is with a reboot.


#ifdef'd code doing all this ^^^^ would be more useful imho.



> + *
> + * Power9 hardware requires [h]srr1 to be set explicitly.
> + *
> + * r3 = 1 if primary thread
> + *      0 if secondary thread
> + */
> +.global exit_uv_mode
> +exit_uv_mode:
> +        mfmsr   %r4
> +        LOAD_IMM64(%r5, ~MSR_S)
> +        and     %r4,%r4,%r5
> +        mtspr   SPR_USRR1,%r4
> +
> +        mfspr   %r4,SPR_HSRR1
> +        and     %r4,%r4,%r5
> +        mtspr   SPR_HSRR1,%r3
> +
> +        mfspr   %r4,SPR_SRR1
> +        and     %r4,%r4,%r5
> +        mtspr   SPR_SRR1,%r4
> +
> +        cmpdi   %r3,1
> +        bne     1f
> +        mfspr   %r4, SPR_SMFCTRL
> +        LOAD_IMM64(%r5, ~PPC_BIT(0))
> +        and     %r4,%r4,%r5
> +        mtspr   SPR_SMFCTRL,%r4
> +1:
> +        isync
> +        mflr    %r4
> +        mtspr   SPR_USRR0,%r4
> +        urfid
> diff --git a/include/processor.h b/include/processor.h
> index f1a88d32..65e4a07b 100644
> --- a/include/processor.h
> +++ b/include/processor.h
> @@ -66,6 +66,9 @@
>  #define SPR_HMEER	0x151	/* HMER interrupt enable mask */
>  #define SPR_PCR		0x152
>  #define SPR_AMOR	0x15d
> +#define SPR_USRR0	0x1fa   /* RW: Ultravisor Save/Restore Register 0 */
> +#define SPR_USRR1	0x1fb   /* RW: Ultravisor Save/Restore Register 1 */
> +#define SPR_SMFCTRL	0x1ff   /* RW: Secure Memory Facility Control */
>  #define SPR_PSSCR	0x357   /* RW: Stop status and control (ISA 3) */
>  #define SPR_TSCR	0x399
>  #define SPR_HID0	0x3f0
> 

-- 
Alexey