[Skiboot] [PATCH 02/11] xive/p9: Clarify the global IRQ number encoding

[Cédric Le Goater]

On 6/8/20 5:31 AM, Gustavo Romero wrote:
> Hi Cédric,
> 
> On 6/4/20 10:21 AM, Cédric Le Goater wrote:
>> On P9, the global IRQ number is limited to 24 bits because the XICS
>> emulation encodes the CPPR value in the top 8 bits. The following
>> 4 bits are used to encode the XIVE block number, which leaves 20 bits
>> for the interrupt index number. Introduce a definition reflecting the
>> size of this bitfield and check that number of interrupts per chip is
>> not overflowing our encoding.
>>
>> Signed-off-by: Cédric Le Goater <clg at kaod.org>
>> ---
>>   hw/xive.c | 13 +++++++++----
>>   1 file changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/xive.c b/hw/xive.c
>> index b9cdc4b0e317..3d016934a96d 100644
>> --- a/hw/xive.c
>> +++ b/hw/xive.c
>> @@ -498,11 +498,16 @@ static uint32_t xive_chip_to_block(uint32_t chip_id)
>>    * Global interrupt numbers for non-escalation interrupts are thus
>>    * limited to 24 bits which is necessary for our XICS emulation since
>>    * the top 8 bits are reserved for the CPPR value.
> 
> I think the commit message is more clear than the comment found in the
> source, so I'm wondering if it's good to replace the comment above with
> something like (taken from the commit message):
> 
>  Global interrupt numbers for non-escalation interrupts are thus
>  limited to 24 bits because the XICS emulation encodes the CPPR
>  value in the top (MSB) 8 bits. Hence, 4 bits are left to the
>  XIVE block number and the remaining 20 bits for the interrupt
>  index number.

Done for v2.

Thanks,

C. 

> Anyway, Reviewed-by: Gustavo Romero <gromero at linux.ibm.com>
> 
> 
> Best regards,
> Gustavo