[Skiboot] [PATCH] npu2-opencapi: don't fence on masked XSL errors

[Frederic Barrat]

Le 08/01/2020 à 01:05, Andrew Donnellan a écrit :
> On 12/12/19 4:07 am, Frederic Barrat wrote:
>> An upcoming change in the initfile is going to modify the default
>> action and fence behavior of some of the NPU FIR2 bits. We're already
>> overriding the settings of most of those. The one exception is for
>> bits 41 and 42, which are XSL errors impacting 2 links that we
>> mask (instead we rely on the subsequent OTL error, which is per link).
>>
>> The new initfile will fence-on-error for bits 41 and 42. And even if
>> the FIRs are masked, the NPU logic could fence the links, which is not
>> what we want. So this patch makes sure we don't fence on the FIRs we
>> want to ignore. It has no effect on existing firmware.
>>
>> Signed-off-by: Frederic Barrat <fbarrat at linux.ibm.com>
> 
> Reviewed-by: Andrew Donnellan <ajd at linux.ibm.com>
> 
>> ---
>>   hw/npu2-opencapi.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c
>> index ed6650f4..3b8b5976 100644
>> --- a/hw/npu2-opencapi.c
>> +++ b/hw/npu2-opencapi.c
>> @@ -1681,6 +1681,7 @@ static int enable_interrupts(struct npu2 *p)
>>       reg = npu2_scom_read(p->chip_id, p->xscom_base, 
>> NPU2_MISC_FENCE_ENABLE2,
>>                    NPU2_MISC_DA_LEN_8B);
>>       reg |= xstop_override;
>> +    reg &= ~(PPC_BIT(41) | PPC_BIT(42));
> 
> We do define macros for these bits which might be more explanatory. A 
> comment might also be helpful...

Arg! I had never seen those! v2 on its way...


>>       npu2_scom_write(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2,
>>               NPU2_MISC_DA_LEN_8B, reg);
>>
>