[Skiboot] VAS: Alloc IRQ and port address for each VAS instance

[Haren Myneni]

Setup IRQ and trigger port for each VAS instance and export these
values through device-tree. Kernel setup IRQ mapping and register
port address for each send window depends on VAS instance.

When NX gets page fault on the request buffer, sends an interrupt
to the kernel and the fault will be handled for the corresponding
send window.
    
Signed-off-by: Sukadev Bhattiprolu <sukadev at linux.vnet.ibm.com>
Signed-off-by: Haren Myneni <haren at us.ibm.com>

diff --git a/doc/device-tree/vas.rst b/doc/device-tree/vas.rst
index 438e45f..d27470d 100644
--- a/doc/device-tree/vas.rst
+++ b/doc/device-tree/vas.rst
@@ -18,6 +18,10 @@ Each VAS node contains: ::
 
   ibm,vas-id: unique identifier for each instance of VAS in the system.
 
+  ibm,vas-irq: IRQ entry for this VAS instance.
+
+  ibm,vas-port: Port address for the IRQ.
+
   reg: contains 8 64-bit fields.
 
         Fields [0] and [1] represent the Hypervisor window context BAR
diff --git a/hw/vas.c b/hw/vas.c
index 212da0e..6096d1c 100644
--- a/hw/vas.c
+++ b/hw/vas.c
@@ -6,6 +6,7 @@
 #include <phys-map.h>
 #include <xscom.h>
 #include <io.h>
+#include <xive.h>
 #include <vas.h>
 
 #define vas_err(__fmt,...)	prlog(PR_ERR,"VAS: " __fmt, ##__VA_ARGS__)
@@ -24,6 +25,7 @@ struct vas {
 	uint64_t	xscom_base;
 	uint64_t	wcbs;
 	uint32_t	vas_irq;
+	uint64_t	vas_port;
 };
 
 static inline void get_hvwc_mmio_bar(int chipid, uint64_t *start, uint64_t *len)
@@ -402,6 +404,8 @@ static void create_mm_dt_node(struct proc_chip *chip)
 
 	dt_add_property(dn, "ibm,vas-id", &vas->vas_id, sizeof(vas->vas_id));
 	dt_add_property(dn, "ibm,chip-id", &gcid, sizeof(gcid));
+	dt_add_property(dn, "ibm,vas-irq", &vas->vas_irq, sizeof(vas->vas_irq));
+	dt_add_property_u64(dn, "ibm,vas-port", vas->vas_port);
 }
 
 /*
@@ -423,6 +427,25 @@ static void disable_vas_inst(struct dt_node *np)
 	reset_north_ctl(chip);
 }
 
+static int vas_setup_irq(struct proc_chip *chip)
+{
+	uint32_t irq;
+	uint64_t port;
+
+	irq = xive_alloc_ipi_irqs(chip->id, 1, 64);
+	if (irq == XIVE_IRQ_ERROR)
+		return -1;
+
+	vas_vdbg("trigger port: 0x%p\n", xive_get_trigger_port(irq));
+
+	port = (uint64_t)xive_get_trigger_port(irq);
+
+	chip->vas->vas_irq = irq;
+	chip->vas->vas_port = port;
+
+	return 0;
+}
+
 /*
  * Initialize one VAS instance and enable it if @enable is true.
  */
@@ -452,6 +475,9 @@ static int init_vas_inst(struct dt_node *np, bool enable)
 	    			init_rma(chip))
 		return -1;
 
+	if (vas_setup_irq(chip))
+		return -1;
+
 	create_mm_dt_node(chip);
 
 	prlog(PR_INFO, "VAS: Initialized chip %d\n", chip->id);