[Skiboot] [PATCH V3]: VAS: Alloc IRQ and port address for each VAS instance

[Haren Myneni]

Setup IRQ and trigger port for each VAS instance. Export these
values through device-tree with 'interrupts' and 'ibm,vas-port'
properties in each VAS device node. Kernel setup IRQ and register
port address for each send window.
    
Signed-off-by: Sukadev Bhattiprolu <sukadev at linux.vnet.ibm.com>
Signed-off-by: Haren Myneni <haren at us.ibm.com>
---
Changelog:
V2: Use standard 'interrupts' property as suggested by Oliver
V3: Do not return if can not allocate interrupt. Needed only
    for user space.

diff --git a/doc/device-tree/vas.rst b/doc/device-tree/vas.rst
index 438e45f..7c11c78 100644
--- a/doc/device-tree/vas.rst
+++ b/doc/device-tree/vas.rst
@@ -18,6 +18,12 @@ Each VAS node contains: ::
 
   ibm,vas-id: unique identifier for each instance of VAS in the system.
 
+  ibm,vas-port: Port address for the interrupt.
+
+  interrupts: <IRQ# level> for this VAS instance.
+
+  interrupt-parent: Interrupt controller phandle.
+
   reg: contains 8 64-bit fields.
 
         Fields [0] and [1] represent the Hypervisor window context BAR
diff --git a/hw/vas.c b/hw/vas.c
index 212da0e..522fb04 100644
--- a/hw/vas.c
+++ b/hw/vas.c
@@ -6,6 +6,8 @@
 #include <phys-map.h>
 #include <xscom.h>
 #include <io.h>
+#include <xive.h>
+#include <interrupts.h>
 #include <vas.h>
 
 #define vas_err(__fmt,...)	prlog(PR_ERR,"VAS: " __fmt, ##__VA_ARGS__)
@@ -24,6 +26,7 @@ struct vas {
 	uint64_t	xscom_base;
 	uint64_t	wcbs;
 	uint32_t	vas_irq;
+	uint64_t	vas_port;
 };
 
 static inline void get_hvwc_mmio_bar(int chipid, uint64_t *start, uint64_t *len)
@@ -402,6 +405,12 @@ static void create_mm_dt_node(struct proc_chip *chip)
 
 	dt_add_property(dn, "ibm,vas-id", &vas->vas_id, sizeof(vas->vas_id));
 	dt_add_property(dn, "ibm,chip-id", &gcid, sizeof(gcid));
+	if (vas->vas_irq) {
+		dt_add_property_cells(dn, "interrupts", vas->vas_irq, 0);
+		dt_add_property_cells(dn, "interrupt-parent",
+					get_ics_phandle());
+		dt_add_property_u64(dn, "ibm,vas-port", vas->vas_port);
+	}
 }
 
 /*
@@ -423,6 +432,27 @@ static void disable_vas_inst(struct dt_node *np)
 	reset_north_ctl(chip);
 }
 
+static void vas_setup_irq(struct proc_chip *chip)
+{
+
+	uint32_t irq;
+	uint64_t port;
+
+	irq = xive_alloc_ipi_irqs(chip->id, 1, 64);
+	if (irq == XIVE_IRQ_ERROR) {
+		vas_err("Failed to allocate interrupt sources for chipID %d\n",
+				chip->id);
+		return;
+	}
+
+	vas_vdbg("trigger port: 0x%p\n", xive_get_trigger_port(irq));
+
+	port = (uint64_t)xive_get_trigger_port(irq);
+
+	chip->vas->vas_irq = irq;
+	chip->vas->vas_port = port;
+}
+
 /*
  * Initialize one VAS instance and enable it if @enable is true.
  */
@@ -452,6 +482,8 @@ static int init_vas_inst(struct dt_node *np, bool enable)
 	    			init_rma(chip))
 		return -1;
 
+	vas_setup_irq(chip);
+
 	create_mm_dt_node(chip);
 
 	prlog(PR_INFO, "VAS: Initialized chip %d\n", chip->id);