[Skiboot] [PATCH v3 14/17] xive/p9: introduce NVT_SHIFT

[Cédric Le Goater]

This defines the size of our VP space which is constrained by the
definition of the END structure in the XIVE architecture for POWER9:

  #define EQ_W6_NVT_BLOCK		PPC_BITMASK32(9,12)
  #define EQ_W6_NVT_INDEX		PPC_BITMASK32(13,31)

The NVT/VP id is returned to the hypervisor by the OPAL call
opal_xive_get_vp_info() and later pushed in W2 of the OS CAM line when
a vCPU is dispatched on an HW thread.

Signed-off-by: Cédric Le Goater <clg at kaod.org>
---
 hw/xive.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/xive.c b/hw/xive.c
index 0156ae66e150..e944e858d128 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -196,7 +196,10 @@
  *
  * XXX Adjust that based on BAR value ?
  */
-#define MAX_VP_ORDER		19	/* 512k */
+
+#define NVT_SHIFT		19	/* in sync with EQ_W6_NVT_INDEX */
+
+#define MAX_VP_ORDER		NVT_SHIFT /* 512k */
 #define MAX_VP_COUNT		(1ul << MAX_VP_ORDER)
 #define VP_PER_PAGE		(0x10000 / 64) // Use sizeof ?
 #define IND_VP_TABLE_SIZE	((MAX_VP_COUNT / VP_PER_PAGE) * 8)
@@ -4049,7 +4052,7 @@ static int64_t opal_xive_get_vp_info(uint64_t vp_id,
 	}
 
 	if (out_cam_value)
-		*out_cam_value = (blk << 19) | idx;
+		*out_cam_value = (blk << NVT_SHIFT) | idx;
 
 	if (out_report_cl_pair) {
 		*out_report_cl_pair = ((uint64_t)(vp->w6 & 0x0fffffff)) << 32;
-- 
2.21.0