[Skiboot] [PATCH v3] core/init: Add ibm, processor-storage-keys property to CPU DT node

Michael Ellerman mpe at ellerman.id.au
Mon Nov 18 13:37:46 AEDT 2019

From: Thiago Jung Bauermann <bauerman at linux.vnet.ibm.com>

LoPAPR says:


    property name indicating the number of virtual storage keys supported
    by the processor described by this node.

    prop-encoded-array: Consists of two cells encoded as with encode-int.
    The first cell represents the number of virtual storage keys supported
    for data accesses while the second cell represents the number of
    virtual storage keys supported for instruction accesses. The cell value
    of zero indicates that no storage keys are supported for the access

pHyp provides the property above but there's a bug in P8 firmware
where the second cell is zero even though POWER8 supports instruction
access keys. This bug will be fixed for P9.

While this is a PAPR property, it's useful to have it in powernv as
well so that Linux has a uniform way of checking for the feature
regardless of the platform it's running on.

Tested on QEMU POWER8 powernv model, Mambo P9 and POWER8 Firenze

Signed-off-by: Thiago Jung Bauermann <bauerman at linux.vnet.ibm.com>
[mpe: Rebase, add comment explaining why we hard code 32]
Signed-off-by: Michael Ellerman <mpe at ellerman.id.au>
 core/init.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/core/init.c b/core/init.c
index e6efb600..950a37b4 100644
--- a/core/init.c
+++ b/core/init.c
@@ -634,6 +634,31 @@ void __noreturn load_and_boot_kernel(bool is_reboot)
 	start_kernel(kernel_entry, fdt, mem_top);
+static void storage_keys_fixup(void)
+	struct dt_node *cpus, *n;
+	cpus = dt_find_by_path(dt_root, "/cpus");
+	assert(cpus);
+	if (proc_gen == proc_gen_unknown)
+		return;
+	dt_for_each_child(cpus, n) {
+		/* There may be cache nodes in /cpus. */
+		if (!dt_has_node_property(n, "device_type", "cpu") ||
+		    dt_has_node_property(n, "ibm,processor-storage-keys", NULL))
+			continue;
+		/*
+		 * skiboot supports p8 & p9, both of which support the IAMR, and
+		 * both of which support 32 keys. So advertise 32 keys for data
+		 * accesses and 32 for instruction accesses.
+		 */
+		dt_add_property_cells(n, "ibm,processor-storage-keys", 32, 32);
+	}
 static void dt_fixups(void)
 	struct dt_node *n;
@@ -661,6 +686,8 @@ static void dt_fixups(void)
 		if (!dt_has_node_property(n, "scom-controller", NULL))
 			dt_add_property(n, "scom-controller", NULL, 0);
+	storage_keys_fixup();
 static void add_arch_vector(void)

More information about the Skiboot mailing list