[Skiboot] [PATCH 8/8] Remove dead POWER7 code
Nicholas Piggin
npiggin at gmail.com
Fri Nov 8 00:52:20 AEDT 2019
There are a number of proc_gen branches removed that are trivially
dead code and comments that refer to P7. As well as those:
- Oliver points out that add_xics_icps() must be unused on POWER8
because it asserts if number of threads > 4, so remove it.
- Change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all
references to opal_boot_trampoline, so remove that.
- It also removed the only non-trival choose_bus implementation, so
that is removed and its caller simplified.
Cc: Stewart Smith <stewart at flamingspork.com>
Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
---
asm/head.S | 10 ------
core/affinity.c | 2 +-
core/direct-controls.c | 12 -------
core/fast-reboot.c | 6 ----
core/pci.c | 43 +++--------------------
hdata/cpu-common.c | 2 +-
hdata/paca.c | 80 ------------------------------------------
hdata/pcia.c | 2 +-
hdata/spira.c | 6 +---
hdata/spira.h | 2 +-
hdata/vpd.c | 1 -
hw/fsp/fsp-console.c | 58 ++++++++++--------------------
hw/fsp/fsp-occ.c | 4 ---
hw/fsp/fsp-sysdump.c | 19 ----------
hw/fsp/fsp.c | 5 +--
hw/npu.c | 1 -
hw/npu2-opencapi.c | 1 -
hw/npu2.c | 1 -
hw/nx-842.c | 11 +++---
hw/occ.c | 8 ++---
hw/phb3.c | 11 ------
hw/phb4.c | 11 ------
hw/psi.c | 3 +-
hw/slw.c | 3 --
hw/xscom.c | 10 +-----
include/chip.h | 4 +--
include/mem-map.h | 2 +-
include/nx.h | 2 +-
include/pci.h | 6 ----
29 files changed, 41 insertions(+), 285 deletions(-)
diff --git a/asm/head.S b/asm/head.S
index 21e653f00..e59f63871 100644
--- a/asm/head.S
+++ b/asm/head.S
@@ -861,16 +861,6 @@ hv_lid_load_table:
.long 0
- /* The FSP seems to ignore our primary/secondary entry
- * points and instead copy that bit down to 0x180 and
- * patch the first instruction to get our expected
- * boot CPU number. We ignore that patching for now and
- * got to the same entry we use for pHyp and FDT HB.
- */
-opal_boot_trampoline:
- li %r27,-1
- ba boot_entry - __head
-
/*
*
* OPAL entry point from operating system
diff --git a/core/affinity.c b/core/affinity.c
index d2bf03095..dabe8930d 100644
--- a/core/affinity.c
+++ b/core/affinity.c
@@ -47,7 +47,7 @@ static uint32_t get_chip_node_id(struct proc_chip *chip)
/*
* Else use the 3 top bits of the chip ID which should be
- * the node on both P7 and P8
+ * the node on P8
*/
return chip->id >> 3;
}
diff --git a/core/direct-controls.c b/core/direct-controls.c
index 507a16f50..424b3d94c 100644
--- a/core/direct-controls.c
+++ b/core/direct-controls.c
@@ -522,9 +522,6 @@ int dctl_set_special_wakeup(struct cpu_thread *t)
struct cpu_thread *c = t->primary;
int rc = OPAL_SUCCESS;
- if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8)
- return OPAL_UNSUPPORTED;
-
lock(&c->dctl_lock);
if (c->special_wakeup_count == 0) {
if (proc_gen == proc_gen_p9)
@@ -544,9 +541,6 @@ int dctl_clear_special_wakeup(struct cpu_thread *t)
struct cpu_thread *c = t->primary;
int rc = OPAL_SUCCESS;
- if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8)
- return OPAL_UNSUPPORTED;
-
lock(&c->dctl_lock);
if (!c->special_wakeup_count)
goto out;
@@ -592,9 +586,6 @@ static int dctl_stop(struct cpu_thread *t)
struct cpu_thread *c = t->primary;
int rc;
- if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8)
- return OPAL_UNSUPPORTED;
-
lock(&c->dctl_lock);
if (t->dctl_stopped) {
unlock(&c->dctl_lock);
@@ -643,9 +634,6 @@ static int dctl_sreset(struct cpu_thread *t)
struct cpu_thread *c = t->primary;
int rc;
- if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8)
- return OPAL_UNSUPPORTED;
-
lock(&c->dctl_lock);
if (!t->dctl_stopped) {
unlock(&c->dctl_lock);
diff --git a/core/fast-reboot.c b/core/fast-reboot.c
index 6de7b068e..410acfe63 100644
--- a/core/fast-reboot.c
+++ b/core/fast-reboot.c
@@ -103,12 +103,6 @@ void fast_reboot(void)
{
static int fast_reboot_count = 0;
- if (!chip_quirk(QUIRK_MAMBO_CALLOUTS) &&
- (proc_gen != proc_gen_p8 && proc_gen != proc_gen_p9)) {
- prlog(PR_DEBUG,
- "RESET: Fast reboot not available on this CPU\n");
- return;
- }
if (chip_quirk(QUIRK_NO_DIRECT_CTL)) {
prlog(PR_DEBUG,
"RESET: Fast reboot disabled by quirk\n");
diff --git a/core/pci.c b/core/pci.c
index 9ee70f4fd..db0f42f56 100644
--- a/core/pci.c
+++ b/core/pci.c
@@ -736,9 +736,8 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
bool scan_downstream)
{
struct pci_device *pd = NULL, *rc = NULL;
- uint8_t dev, fn, next_bus, max_sub, save_max;
+ uint8_t dev, fn, next_bus, max_sub;
uint32_t scan_map;
- bool use_max;
/* Decide what to scan */
scan_map = parent ? parent->scan_map : phb->scan_map;
@@ -772,8 +771,7 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
* if PCI hotplug is supported.
*/
if (rc && rc->slot && rc->slot->pluggable) {
- next_bus = phb->ops->choose_bus(phb, rc, bus + 1,
- &max_bus, &use_max);
+ next_bus = bus + 1;
rc->secondary_bus = next_bus;
rc->subordinate_bus = max_bus;
pci_cfg_write8(phb, rc->bdfn, PCI_CFG_SECONDARY_BUS,
@@ -803,7 +801,6 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
next_bus = bus + 1;
max_sub = bus;
- save_max = max_bus;
/* Scan down bridges */
list_for_each(list, pd, link) {
@@ -812,33 +809,6 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
if (!pd->is_bridge)
continue;
- /* We need to figure out a new bus number to start from.
- *
- * This can be tricky due to our HW constraints which differ
- * from bridge to bridge so we are going to let the phb
- * driver decide what to do. This can return us a maximum
- * bus number to assign as well
- *
- * This function will:
- *
- * - Return the bus number to use as secondary for the
- * bridge or 0 for a failure
- *
- * - "max_bus" will be adjusted to represent the max
- * subordinate that can be associated with the downstream
- * device
- *
- * - "use_max" will be set to true if the returned max_bus
- * *must* be used as the subordinate bus number of that
- * bridge (when we need to give aligned powers of two's
- * on P7IOC). If is is set to false, we just adjust the
- * subordinate bus number based on what we probed.
- *
- */
- max_bus = save_max;
- next_bus = phb->ops->choose_bus(phb, pd, next_bus,
- &max_bus, &use_max);
-
/* Configure the bridge with the returned values */
if (next_bus <= bus) {
PCIERR(phb, pd->bdfn, "Out of bus numbers !\n");
@@ -852,8 +822,8 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
if (!next_bus)
break;
- PCIDBG(phb, pd->bdfn, "Bus %02x..%02x %s scanning...\n",
- next_bus, max_bus, use_max ? "[use max]" : "");
+ PCIDBG(phb, pd->bdfn, "Bus %02x..%02x scanning...\n",
+ next_bus, max_bus);
/* Clear up bridge resources */
pci_cleanup_bridge(phb, pd);
@@ -869,7 +839,7 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
if (do_scan) {
max_sub = pci_scan_bus(phb, next_bus, max_bus,
&pd->children, pd, true);
- } else if (!use_max) {
+ } else {
/* Empty bridge. We leave room for hotplug
* slots if the downstream port is pluggable.
*/
@@ -882,9 +852,6 @@ uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
}
}
- /* Update the max subordinate as described previously */
- if (use_max)
- max_sub = max_bus;
pd->subordinate_bus = max_sub;
pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SUBORDINATE_BUS, max_sub);
next_bus = max_sub + 1;
diff --git a/hdata/cpu-common.c b/hdata/cpu-common.c
index 55a663fa4..20fad5c03 100644
--- a/hdata/cpu-common.c
+++ b/hdata/cpu-common.c
@@ -107,7 +107,7 @@ struct dt_node * add_core_common(struct dt_node *cpus,
dt_add_property_cells(cpu, "ibm,processor-radix-AP-encodings",
0x0000000c, 0xa0000010, 0x20000015, 0x4000001e);
- /* Page size encodings appear to be the same for P7 and P8 */
+ /* HPT segment page size encodings, common to all supported CPUs */
dt_add_property_cells(cpu, "ibm,segment-page-sizes",
0x0c, 0x000, 3, 0x0c, 0x0000, /* 4K seg 4k pages */
0x10, 0x0007, /* 4K seg 64k pages */
diff --git a/hdata/paca.c b/hdata/paca.c
index 28025b0cd..3e8d89856 100644
--- a/hdata/paca.c
+++ b/hdata/paca.c
@@ -12,8 +12,6 @@
#include "hdata.h"
-#define PACA_MAX_THREADS 4
-
static unsigned int paca_index(const struct HDIF_common_hdr *paca)
{
void *start = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG);
@@ -121,77 +119,6 @@ static void add_be32_sorted(__be32 arr[], __be32 new, unsigned num)
arr[i] = new;
}
-static void add_xics_icps(void)
-{
- struct dt_node *cpu;
- unsigned int i;
- u64 reg[PACA_MAX_THREADS * 2];
- struct dt_node *icp;
-
- dt_for_each_node(dt_root, cpu) {
- u32 irange[2], size, pir;
- const struct dt_property *intsrv;
- const struct HDIF_common_hdr *paca;
- u64 ibase;
- unsigned int num_threads;
- bool found = false;
-
- if (!dt_has_node_property(cpu, "device_type", "cpu"))
- continue;
-
- intsrv = dt_find_property(cpu, "ibm,ppc-interrupt-server#s");
- if (!intsrv)
- continue;
-
- pir = dt_prop_get_u32(cpu, "ibm,pir");
-
- /* Get ibase address */
- paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG);
- for_each_paca(paca) {
- const struct sppaca_cpu_id *id;
- id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size);
-
- if (!CHECK_SPPTR(id))
- continue;
-
- if (pir != be32_to_cpu(id->pir))
- continue;
- ibase = cleanup_addr(be64_to_cpu(id->ibase));
- found = true;
- break;
- }
- if (!found)
- return;
-
- num_threads = intsrv->len / sizeof(u32);
- assert(num_threads <= PACA_MAX_THREADS);
-
- icp = dt_new_addr(dt_root, "interrupt-controller", ibase);
- if (!icp)
- continue;
-
- dt_add_property_strings(icp, "compatible",
- "IBM,ppc-xicp",
- "IBM,power7-xicp");
-
- irange[0] = dt_property_get_cell(intsrv, 0); /* Index */
- irange[1] = num_threads; /* num servers */
- dt_add_property(icp, "ibm,interrupt-server-ranges",
- irange, sizeof(irange));
- dt_add_property(icp, "interrupt-controller", NULL, 0);
- dt_add_property_cells(icp, "#address-cells", 0);
- dt_add_property_string(icp, "device_type",
- "PowerPC-External-Interrupt-Presentation");
- for (i = 0; i < num_threads*2; i += 2) {
- reg[i] = ibase;
- /* One page is enough for a handful of regs. */
- reg[i+1] = 4096;
- ibase += reg[i+1];
- }
- dt_add_property(icp, "reg", reg, sizeof(reg));
- }
-}
-
static bool __paca_parse(void)
{
const struct HDIF_common_hdr *paca;
@@ -311,13 +238,6 @@ static bool __paca_parse(void)
free(new_prop);
}
- /*
- * P7 and P8 use the XICS interrupt controller which has a per-core
- * interrupt controller node.
- */
- if (proc_gen <= proc_gen_p8)
- add_xics_icps();
-
return true;
}
diff --git a/hdata/pcia.c b/hdata/pcia.c
index ff645aba6..04f90b954 100644
--- a/hdata/pcia.c
+++ b/hdata/pcia.c
@@ -168,7 +168,7 @@ static struct dt_node *add_core_node(struct dt_node *cpus,
dt_add_property(cpu, "ibm,ppc-interrupt-server#s", iserv, 4 * threads);
/* Add the ICP node for this CPU for P8 */
- if (proc_gen <= proc_gen_p8)
+ if (proc_gen == proc_gen_p8)
add_xics_icp(pcia, threads, icp_compat);
return cpu;
diff --git a/hdata/spira.c b/hdata/spira.c
index 5e73b7d44..82f9f7b73 100644
--- a/hdata/spira.c
+++ b/hdata/spira.c
@@ -847,7 +847,7 @@ static void add_nx_node(u32 gcid)
"ibm,power8-nx");
break;
case proc_gen_p9:
- /* POWER9 NX is not software compatible with P7/P8 NX */
+ /* POWER9 NX is not software compatible with P8 NX */
dt_add_property_strings(nx, "compatible", "ibm,power9-nx");
break;
default:
@@ -1294,10 +1294,6 @@ static void add_iplparams(void)
* numbering used by HDAT to reference chips, which doesn't correspond
* to the HW IDs. We want to use the HW IDs everywhere in the DT so
* we convert using this.
- *
- * Note: On P7, the HW ID is the XSCOM "GCID" including the T bit which
- * is *different* from the chip ID portion of the interrupt server#
- * (or PIR). See the explanations in chip.h
*/
uint32_t pcid_to_chip_id(uint32_t proc_chip_id)
{
diff --git a/hdata/spira.h b/hdata/spira.h
index eb5d1ea1b..107c9a91d 100644
--- a/hdata/spira.h
+++ b/hdata/spira.h
@@ -73,7 +73,7 @@ struct spira {
struct spira_ntuples ntuples;
/*
* We reserve 0xc0 rather than 0x4c0 so we fit SPIRAH/SPIRAS here
- * while preserving compatibility with existing P7/P8 systems.
+ * while preserving compatibility with existing P8 systems.
*
* According to FSP engineers, this is an okay thing to do.
*/
diff --git a/hdata/vpd.c b/hdata/vpd.c
index a29155a36..3c480b444 100644
--- a/hdata/vpd.c
+++ b/hdata/vpd.c
@@ -702,7 +702,6 @@ static void iohub_vpd_parse(void)
continue;
}
- /* On P7, the keyword VPD will not be NULL */
if (HDIF_get_idata(iohub_hdr,
CECHUB_ASCII_KEYWORD_VPD, &vpd_sz))
dt_add_vpd_node(iohub_hdr, CECHUB_FRU_ID_DATA,
diff --git a/hw/fsp/fsp-console.c b/hw/fsp/fsp-console.c
index 42fb98806..1a2ecaba0 100644
--- a/hw/fsp/fsp-console.c
+++ b/hw/fsp/fsp-console.c
@@ -1015,53 +1015,31 @@ void fsp_console_add_nodes(void)
void fsp_console_select_stdout(void)
{
bool use_serial = false;
+ int rc;
+ u8 param;
if (!fsp_present())
return;
- /* On P8, we have a sysparam ! yay ! */
- if (proc_gen >= proc_gen_p8) {
- int rc;
- u8 param;
-
- rc = fsp_get_sys_param(SYS_PARAM_CONSOLE_SELECT,
- ¶m, 1, NULL, NULL);
- if (rc != 1)
- prerror("FSPCON: Failed to get console"
- " sysparam rc %d\n", rc);
- else {
- switch(param) {
- case 0:
- use_serial = false;
- break;
- case 1:
- use_serial = true;
- break;
- default:
- prerror("FSPCON: Unknown console"
- " sysparam %d\n", param);
- }
- }
+ rc = fsp_get_sys_param(SYS_PARAM_CONSOLE_SELECT,
+ ¶m, 1, NULL, NULL);
+ if (rc != 1) {
+ prerror("FSPCON: Failed to get console"
+ " sysparam rc %d\n", rc);
} else {
- struct dt_node *iplp;
- u32 ipl_mode = 0;
-
- /*
- * We hijack the "os-ipl-mode" setting in iplparams to select
- * out output console. This is the "i5/OS partition mode boot"
- * setting in ASMI converted to an integer: 0=A, 1=B.
- */
- iplp = dt_find_by_path(dt_root, "ipl-params/ipl-params");
- if (iplp) {
- ipl_mode = dt_prop_get_u32_def(iplp, "os-ipl-mode", 0);
- use_serial = ipl_mode > 0;
-
- /*
- * Now, if ipl_mode is > 0, we use serial port A else
- * we use IPMI/SOL/DVS
- */
+ switch(param) {
+ case 0:
+ use_serial = false;
+ break;
+ case 1:
+ use_serial = true;
+ break;
+ default:
+ prerror("FSPCON: Unknown console"
+ " sysparam %d\n", param);
}
}
+
dt_check_del_prop(dt_chosen, "linux,stdout-path");
if (fsp_serials[1].open && use_serial) {
diff --git a/hw/fsp/fsp-occ.c b/hw/fsp/fsp-occ.c
index d48c28f8a..8164129e9 100644
--- a/hw/fsp/fsp-occ.c
+++ b/hw/fsp/fsp-occ.c
@@ -410,10 +410,6 @@ static struct fsp_client fsp_occ_client = {
void occ_fsp_init(void)
{
- /* OCC is supported in P8 and P9 */
- if (proc_gen < proc_gen_p8)
- return;
-
/* If we have an FSP, register for notifications */
if (fsp_present())
fsp_register_client(&fsp_occ_client, FSP_MCLASS_OCC);
diff --git a/hw/fsp/fsp-sysdump.c b/hw/fsp/fsp-sysdump.c
index cf4af34d1..fd915f402 100644
--- a/hw/fsp/fsp-sysdump.c
+++ b/hw/fsp/fsp-sysdump.c
@@ -64,12 +64,6 @@ static int max_dump_size = MIN(MAX_SAPPHIRE_DUMP_SIZE, PSI_DMA_HYP_DUMP_SIZE);
/* Protect MDST table entries */
static struct lock mdst_lock = LOCK_UNLOCKED;
-/* Not supported on P7 */
-static inline bool fsp_mdst_supported(void)
-{
- return proc_gen >= proc_gen_p8;
-}
-
static inline uint32_t get_dump_region_map_size(uint64_t addr, uint32_t size)
{
uint64_t start, end;
@@ -280,11 +274,6 @@ static int64_t fsp_opal_register_dump_region(uint32_t id,
if (!fsp_present())
return OPAL_UNSUPPORTED;
- if (!fsp_mdst_supported()) {
- printf("MDST: Not supported\n");
- return OPAL_UNSUPPORTED;
- }
-
/* Validate memory region id */
if (id < DUMP_REGION_HOST_START || id > DUMP_REGION_HOST_END) {
log_simple_error(&e_info(OPAL_RC_DUMP_MDST_ADD),
@@ -315,11 +304,6 @@ static int64_t fsp_opal_unregister_dump_region(uint32_t id)
if (!fsp_present())
return OPAL_UNSUPPORTED;
- if (!fsp_mdst_supported()) {
- printf("MDST: Not supported\n");
- return OPAL_UNSUPPORTED;
- }
-
/* Validate memory region id */
if (id < DUMP_REGION_HOST_START || id > DUMP_REGION_HOST_END) {
log_simple_error(&e_info(OPAL_RC_DUMP_MDST_REMOVE),
@@ -407,9 +391,6 @@ void fsp_mdst_table_init(void)
opal_register(OPAL_UNREGISTER_DUMP_REGION,
fsp_opal_unregister_dump_region, 1);
- if (!fsp_mdst_supported())
- return;
-
/* Initiate MDST */
if (mdst_table_init() != OPAL_SUCCESS)
return;
diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c
index 6fa6534f9..f368998fb 100644
--- a/hw/fsp/fsp.c
+++ b/hw/fsp/fsp.c
@@ -1844,10 +1844,7 @@ static void fsp_init_tce_table(void)
{
fsp_tce_table = (u64 *)PSI_TCE_TABLE_BASE;
- /* Memset the larger table even if we only use the smaller
- * one on P7
- */
- memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE_P8);
+ memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE);
}
void fsp_tce_map(u32 offset, void *addr, u32 size)
diff --git a/hw/npu.c b/hw/npu.c
index 31eb8f0ce..cf971bd96 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -988,7 +988,6 @@ static const struct phb_ops npu_ops = {
.cfg_write8 = npu_cfg_write8,
.cfg_write16 = npu_cfg_write16,
.cfg_write32 = npu_cfg_write32,
- .choose_bus = NULL,
.get_reserved_pe_number = NULL,
.device_init = NULL,
.phb_final_fixup = npu_phb_final_fixup,
diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c
index fc9e50c3f..a396c2bf5 100644
--- a/hw/npu2-opencapi.c
+++ b/hw/npu2-opencapi.c
@@ -1862,7 +1862,6 @@ static const struct phb_ops npu2_opencapi_ops = {
.cfg_write8 = npu2_opencapi_pcicfg_write8,
.cfg_write16 = npu2_opencapi_pcicfg_write16,
.cfg_write32 = npu2_opencapi_pcicfg_write32,
- .choose_bus = NULL,
.device_init = NULL,
.phb_final_fixup = npu2_opencapi_final_fixup,
.ioda_reset = npu2_opencapi_ioda_reset,
diff --git a/hw/npu2.c b/hw/npu2.c
index 81539d1ae..aeb7c49ec 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -1292,7 +1292,6 @@ static const struct phb_ops npu_ops = {
.cfg_write8 = npu2_cfg_write8,
.cfg_write16 = npu2_cfg_write16,
.cfg_write32 = npu2_cfg_write32,
- .choose_bus = NULL,
.device_init = NULL,
.phb_final_fixup = npu2_phb_final_fixup,
.ioda_reset = npu2_ioda_reset,
diff --git a/hw/nx-842.c b/hw/nx-842.c
index fd6f74caa..933f2df13 100644
--- a/hw/nx-842.c
+++ b/hw/nx-842.c
@@ -118,13 +118,10 @@ static int nx_cfg_842_dma(u32 gcid, u64 xcfg)
return rc;
}
- if (proc_gen >= proc_gen_p8) {
- cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg,
- DMA_COMPRESS_PREFETCH);
- cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg,
- DMA_DECOMPRESS_PREFETCH);
- }
-
+ cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg,
+ DMA_COMPRESS_PREFETCH);
+ cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg,
+ DMA_DECOMPRESS_PREFETCH);
cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_MAX_RR, cfg,
DMA_COMPRESS_MAX_RR);
cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_MAX_RR, cfg,
diff --git a/hw/occ.c b/hw/occ.c
index db2744ff7..2c989a616 100644
--- a/hw/occ.c
+++ b/hw/occ.c
@@ -1719,10 +1719,6 @@ void occ_pstates_init(void)
u8 domain_runs_at;
static bool occ_pstates_initialized;
- /* OCC is supported in P8 and P9 */
- if (proc_gen < proc_gen_p8)
- return;
-
power_mgt = dt_find_by_path(dt_root, "/ibm,opal/power-mgt");
if (!power_mgt) {
/**
@@ -1969,8 +1965,8 @@ void occ_send_dummy_interrupt(void)
struct psi *psi;
struct proc_chip *chip = get_chip(this_cpu()->chip_id);
- /* Emulators and P7 doesn't do this */
- if (proc_gen < proc_gen_p8 || chip_quirk(QUIRK_NO_OCC_IRQ))
+ /* Emulators don't do this */
+ if (chip_quirk(QUIRK_NO_OCC_IRQ))
return;
/* Find a functional PSI. This ensures an interrupt even if
diff --git a/hw/phb3.c b/hw/phb3.c
index efa8ad179..aa439ee43 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -336,16 +336,6 @@ PHB3_PCI_CFG_WRITE(8, u8)
PHB3_PCI_CFG_WRITE(16, u16)
PHB3_PCI_CFG_WRITE(32, u32)
-static uint8_t phb3_choose_bus(struct phb *phb __unused,
- struct pci_device *bridge __unused,
- uint8_t candidate, uint8_t *max_bus __unused,
- bool *use_max)
-{
- /* Use standard bus number selection */
- *use_max = false;
- return candidate;
-}
-
static int64_t phb3_get_reserved_pe_number(struct phb *phb __unused)
{
return PHB3_RESERVED_PE_NUM;
@@ -3857,7 +3847,6 @@ static const struct phb_ops phb3_ops = {
.cfg_write8 = phb3_pcicfg_write8,
.cfg_write16 = phb3_pcicfg_write16,
.cfg_write32 = phb3_pcicfg_write32,
- .choose_bus = phb3_choose_bus,
.get_reserved_pe_number = phb3_get_reserved_pe_number,
.device_init = phb3_device_init,
.device_remove = phb3_device_remove,
diff --git a/hw/phb4.c b/hw/phb4.c
index f02e675f0..4177589b4 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -601,16 +601,6 @@ PHB4_PCI_CFG_WRITE(8, u8)
PHB4_PCI_CFG_WRITE(16, u16)
PHB4_PCI_CFG_WRITE(32, u32)
-static uint8_t phb4_choose_bus(struct phb *phb __unused,
- struct pci_device *bridge __unused,
- uint8_t candidate, uint8_t *max_bus __unused,
- bool *use_max)
-{
- /* Use standard bus number selection */
- *use_max = false;
- return candidate;
-}
-
static int64_t phb4_get_reserved_pe_number(struct phb *phb)
{
struct phb4 *p = phb_to_phb4(phb);
@@ -4795,7 +4785,6 @@ static const struct phb_ops phb4_ops = {
.cfg_write8 = phb4_pcicfg_write8,
.cfg_write16 = phb4_pcicfg_write16,
.cfg_write32 = phb4_pcicfg_write32,
- .choose_bus = phb4_choose_bus,
.get_reserved_pe_number = phb4_get_reserved_pe_number,
.device_init = phb4_device_init,
.device_remove = NULL,
diff --git a/hw/psi.c b/hw/psi.c
index bc170bbcf..73e49ceb7 100644
--- a/hw/psi.c
+++ b/hw/psi.c
@@ -818,7 +818,8 @@ static void psi_create_mm_dtnode(struct psi *psi)
psi_create_p9_int_map(psi, np);
break;
default:
- dt_add_property_strings(np, "compatible", "ibm,psi");
+ assert(0);
+ break;
}
dt_add_property_cells(np, "interrupt-parent", get_ics_phandle());
dt_add_property_cells(np, "interrupts", psi->interrupt, 1);
diff --git a/hw/slw.c b/hw/slw.c
index e460f15ab..566a1128b 100644
--- a/hw/slw.c
+++ b/hw/slw.c
@@ -1061,9 +1061,6 @@ int64_t slw_reinit(uint64_t flags)
bool has_waker = false;
bool target_le = slw_current_le;
- if (proc_gen < proc_gen_p8)
- return OPAL_UNSUPPORTED;
-
if (flags & OPAL_REINIT_CPUS_HILE_BE)
target_le = false;
if (flags & OPAL_REINIT_CPUS_HILE_LE)
diff --git a/hw/xscom.c b/hw/xscom.c
index 9b28422d2..f3f4e1039 100644
--- a/hw/xscom.c
+++ b/hw/xscom.c
@@ -61,7 +61,7 @@ static inline void *xscom_addr(uint32_t gcid, uint32_t pcb_addr)
assert(chip);
addr = chip->xscom_base;
- if (proc_gen <= proc_gen_p8) {
+ if (proc_gen == proc_gen_p8) {
addr |= ((uint64_t)pcb_addr << 4) & ~0xfful;
addr |= (pcb_addr << 3) & 0x78;
} else
@@ -432,11 +432,6 @@ static int xscom_indirect_read_form0(uint32_t gcid, uint64_t pcb_addr,
uint64_t data;
int rc, retries;
- if (proc_gen < proc_gen_p8) {
- *val = (uint64_t)-1;
- return OPAL_UNSUPPORTED;
- }
-
/* Write indirect address */
addr = pcb_addr & 0x7fffffff;
data = XSCOM_DATA_IND_READ |
@@ -491,9 +486,6 @@ static int xscom_indirect_write_form0(uint32_t gcid, uint64_t pcb_addr,
uint64_t data;
int rc, retries;
- if (proc_gen < proc_gen_p8)
- return OPAL_UNSUPPORTED;
-
/* Only 16 bit data with indirect */
if (val & ~(XSCOM_ADDR_IND_DATA))
return OPAL_PARAMETER;
diff --git a/include/chip.h b/include/chip.h
index adb962af8..f14e78b32 100644
--- a/include/chip.h
+++ b/include/chip.h
@@ -34,9 +34,7 @@
* | | |
* |___|___|___|___|___|___|
*
- * The difference with P7 is the absence of T bit, the ChipID
- * is 3 bits long. The GCID is thus the same as the high bits
- * if the PIR
+ * The the ChipID is 3 bits long, the GCID is the same as the high bits of PIR
*/
#define P8_PIR2GCID(pir) (((pir) >> 7) & 0x3f)
diff --git a/include/mem-map.h b/include/mem-map.h
index 991465190..61ecac3c8 100644
--- a/include/mem-map.h
+++ b/include/mem-map.h
@@ -99,7 +99,7 @@
/* This is our PSI TCE table. It's 256K entries on P8 */
#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000)
-#define PSI_TCE_TABLE_SIZE_P8 0x00200000UL
+#define PSI_TCE_TABLE_SIZE 0x00200000UL
/* This is our dump result table after MPIPL. Hostboot will write to this
* memory after moving memory content from source to destination memory.
diff --git a/include/nx.h b/include/nx.h
index 675d17ace..4950a2d86 100644
--- a/include/nx.h
+++ b/include/nx.h
@@ -86,7 +86,7 @@
#define NX_EE_CFG_CH7 PPC_BIT(53) /* AMF */
#define NX_EE_CFG_CH6 PPC_BIT(54) /* AMF */
#define NX_EE_CFG_CH5 PPC_BIT(55) /* AMF */
-#define NX_EE_CFG_CH4 PPC_BIT(56) /* P7: SYM, P8: AMF */
+#define NX_EE_CFG_CH4 PPC_BIT(56) /* AMF */
#define NX_EE_CFG_CH3 PPC_BIT(57) /* SYM */
#define NX_EE_CFG_CH2 PPC_BIT(58) /* SYM */
#define NX_P9_EE_CFG_CH4 PPC_BIT(61) /* gzip */
diff --git a/include/pci.h b/include/pci.h
index 8169fe6a9..fb91d7936 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -218,12 +218,6 @@ struct phb_ops {
int64_t (*cfg_write32)(struct phb *phb, uint32_t bdfn,
uint32_t offset, uint32_t data);
- /*
- * Bus number selection. See pci_scan() for a description
- */
- uint8_t (*choose_bus)(struct phb *phb, struct pci_device *bridge,
- uint8_t candidate, uint8_t *max_bus,
- bool *use_max);
int64_t (*get_reserved_pe_number)(struct phb *phb);
/*
--
2.23.0
More information about the Skiboot
mailing list