[Skiboot] [EXTERNAL] Re: [PATCH skiboot] hmi/npu2: Define macros for registers
Alexey Kardashevskiy
aik at ozlabs.ru
Tue May 21 12:59:13 AEST 2019
On 20/05/2019 14:57, Andrew Donnellan wrote:
> On 20/5/19 2:42 pm, Alexey Kardashevskiy wrote:
>>>>> I'll try and get the next version of that series done sometime in the
>>>>> next 2 weeks or so, but depends when I can get hardware set up in the
>>>>> right configurations I need as we've just had the machine we were
>>>>> using
>>>>> taken from us...
>>>>
>>>>
>>>>
>>>> Ping? Can my patch go in as there is no other alternative yet?
>>>>
>>>
>>> still working on it, delayed by test hardware unavailability - the
>>> machine I needed disappeared from us for other purposes.
>>
>>
>> And? Ack/nack/why?
>
> No objections to this patch but I'm still intending to replace it with
> the more OpenCAPI-friendly approach per the patches that I've already
> sent, it'll just make my rebase harder.
>
> (the v3 of that series has been delayed by a failure in IBM's
> procurement systems, we were meant to have the additional card we needed
> to test fixes to that series weeks ago but as I found out just the other
> day, the order wasn't placed correctly so it still hasn't arrived in the
> France lab. Oh well.)
"Procurement" means this has a good change not to happen in the next 6
months. So we cannot change this code to avoid making your rebase
harder, is that what you are saying? ;)
>
>>
>>
>>
>>
>>>
>>>>
>>>>
>>>>>>
>>>>>>
>>>>>>>
>>>>>>>> ---
>>>>>>>>
>>>>>>>> Warning: this is made on top of just posted
>>>>>>>> "[PATCH skiboot] npu2: Allow disabling Probe.I.MO snarfing"
>>>>>>>> and won't apply otherwise (the conflict is trivial though).
>>>>>>>>
>>>>>>>> ---
>>>>>>>> include/npu2-regs.h | 25 +++++++++++++++
>>>>>>>> hw/npu2.c | 74
>>>>>>>> +++++++++++++++++++++++++--------------------
>>>>>>>> 2 files changed, 67 insertions(+), 32 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/include/npu2-regs.h b/include/npu2-regs.h
>>>>>>>> index 61e8ea8615f8..49b4b97713b5 100644
>>>>>>>> --- a/include/npu2-regs.h
>>>>>>>> +++ b/include/npu2-regs.h
>>>>>>>> @@ -805,4 +805,29 @@ void npu2_scom_write(uint64_t gcid, uint64_t
>>>>>>>> scom_base,
>>>>>>>> #define NPU_STCK2_CS_SM2_MISC_CONFIG0 0x5011460
>>>>>>>> #define NPU_STCK2_CS_SM3_MISC_CONFIG0 0x5011490
>>>>>>>> +#define NPU_STCK0_CS_CTL_MISC_CONFIG0 0x50110C0
>>>>>>>> +#define NPU_STCK1_CS_CTL_MISC_CONFIG0 0x50112C0
>>>>>>>> +#define NPU_STCK2_CS_CTL_MISC_CONFIG0 0x50114C0
>>>>>>>> +#define NPU_STCK0_DAT_MISC_CONFIG1 0x50110F1
>>>>>>>> +#define NPU_STCK1_DAT_MISC_CONFIG1 0x50112F1
>>>>>>>> +#define NPU_STCK2_DAT_MISC_CONFIG1 0x50114F1
>>>>>>>> +#define NPU_STCK0_NTL0_REGS_CONFIG2 0x5011110
>>>>>>>> +#define NPU_STCK0_NTL1_REGS_CONFIG2 0x5011130
>>>>>>>> +#define NPU_STCK1_NTL0_REGS_CONFIG2 0x5011310
>>>>>>>> +#define NPU_STCK1_NTL1_REGS_CONFIG2 0x5011330
>>>>>>>> +#define NPU_STCK2_NTL0_REGS_CONFIG2 0x5011510
>>>>>>>> +#define NPU_STCK2_NTL1_REGS_CONFIG2 0x5011530
>>>>>>>> +#define NPU_STCK0_CS_SM0_MISC_HIGH_WATER 0x5011009
>>>>>>>> +#define NPU_STCK0_CS_SM1_MISC_HIGH_WATER 0x5011039
>>>>>>>> +#define NPU_STCK0_CS_SM2_MISC_HIGH_WATER 0x5011069
>>>>>>>> +#define NPU_STCK0_CS_SM3_MISC_HIGH_WATER 0x5011099
>>>>>>>> +#define NPU_STCK1_CS_SM0_MISC_HIGH_WATER 0x5011209
>>>>>>>> +#define NPU_STCK1_CS_SM1_MISC_HIGH_WATER 0x5011239
>>>>>>>> +#define NPU_STCK1_CS_SM2_MISC_HIGH_WATER 0x5011269
>>>>>>>> +#define NPU_STCK1_CS_SM3_MISC_HIGH_WATER 0x5011299
>>>>>>>> +#define NPU_STCK2_CS_SM0_MISC_HIGH_WATER 0x5011409
>>>>>>>> +#define NPU_STCK2_CS_SM1_MISC_HIGH_WATER 0x5011439
>>>>>>>> +#define NPU_STCK2_CS_SM2_MISC_HIGH_WATER 0x5011469
>>>>>>>> +#define NPU_STCK2_CS_SM3_MISC_HIGH_WATER 0x5011499
>>>>>>>> +
>>>>>>>> #endif /* __NPU2_REGS_H */
>>>>>>>> diff --git a/hw/npu2.c b/hw/npu2.c
>>>>>>>> index c7b7b071f3e0..033d2f04e7a5 100644
>>>>>>>> --- a/hw/npu2.c
>>>>>>>> +++ b/hw/npu2.c
>>>>>>>> @@ -1454,14 +1454,6 @@ int npu2_nvlink_init_npu(struct npu2 *npu)
>>>>>>>> struct dt_node *np;
>>>>>>>> uint64_t reg[2], mm_win[2], val, mask;
>>>>>>>> - /* TODO: Clean this up with register names, etc. when
>>>>>>>> we get
>>>>>>>> - * time. This just turns NVLink mode on in each brick and
>>>>>>>> should
>>>>>>>> - * get replaced with a patch from ajd once we've worked out
>>>>>>>> how
>>>>>>>> - * things are going to work there.
>>>>>>>> - *
>>>>>>>> - * Obviously if the year is now 2020 that didn't happen and
>>>>>>>> you
>>>>>>>> - * should fix this :-) */
>>>>>>>> -
>>>>>>>> val = PPC_BIT(58);
>>>>>>>> mask = PPC_BIT(58); /* CONFIG_NVLINK_MODE */
>>>>>>>> @@ -1493,37 +1485,55 @@ int npu2_nvlink_init_npu(struct npu2
>>>>>>>> *npu)
>>>>>>>> xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK2_CS_SM3_MISC_CONFIG0,
>>>>>>>> val, mask);
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x50110c0, PPC_BIT(53),
>>>>>>>> PPC_BIT(53));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x50112c0, PPC_BIT(53),
>>>>>>>> PPC_BIT(53));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x50114c0, PPC_BIT(53),
>>>>>>>> PPC_BIT(53));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x50110f1, PPC_BIT(41),
>>>>>>>> PPC_BIT(41));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x50112f1, PPC_BIT(41),
>>>>>>>> PPC_BIT(41));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x50114f1, PPC_BIT(41),
>>>>>>>> PPC_BIT(41));
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK0_CS_CTL_MISC_CONFIG0,
>>>>>>>> + PPC_BIT(53), PPC_BIT(53));
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK1_CS_CTL_MISC_CONFIG0,
>>>>>>>> + PPC_BIT(53), PPC_BIT(53));
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK2_CS_CTL_MISC_CONFIG0,
>>>>>>>> + PPC_BIT(53), PPC_BIT(53));
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK0_DAT_MISC_CONFIG1,
>>>>>>>> + PPC_BIT(41), PPC_BIT(41));
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK1_DAT_MISC_CONFIG1,
>>>>>>>> + PPC_BIT(41), PPC_BIT(41));
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK2_DAT_MISC_CONFIG1,
>>>>>>>> + PPC_BIT(41), PPC_BIT(41));
>>>>>>>> val = NPU2_NTL_MISC_CFG2_BRICK_ENABLE |
>>>>>>>> NPU2_NTL_MISC_CFG2_NDL_TX_PARITY_ENA |
>>>>>>>> NPU2_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA |
>>>>>>>> NPU2_NTL_MISC_CFG2_RCV_CREDIT_OVERFLOW_ENA;
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011110, val, val);
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011130, val, val);
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011310, val, val);
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011330, val, val);
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011510, val, val);
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011530, val, val);
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK0_NTL0_REGS_CONFIG2,
>>>>>>>> val,
>>>>>>>> val);
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK0_NTL1_REGS_CONFIG2,
>>>>>>>> val,
>>>>>>>> val);
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK1_NTL0_REGS_CONFIG2,
>>>>>>>> val,
>>>>>>>> val);
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK1_NTL1_REGS_CONFIG2,
>>>>>>>> val,
>>>>>>>> val);
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK2_NTL0_REGS_CONFIG2,
>>>>>>>> val,
>>>>>>>> val);
>>>>>>>> + xscom_write_mask(npu->chip_id, NPU_STCK2_NTL1_REGS_CONFIG2,
>>>>>>>> val,
>>>>>>>> val);
>>>>>>>> val = PPC_BIT(6) | PPC_BIT(7) | PPC_BIT(11);
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011009, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011039, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011069, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011099, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011209, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011239, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011269, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011299, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011409, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011439, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011469, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> - xscom_write_mask(npu->chip_id, 0x5011499, val,
>>>>>>>> PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK0_CS_SM0_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK0_CS_SM1_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK0_CS_SM2_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK0_CS_SM3_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK1_CS_SM0_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK1_CS_SM1_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK1_CS_SM2_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK1_CS_SM3_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK2_CS_SM0_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK2_CS_SM1_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK2_CS_SM2_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> + xscom_write_mask(npu->chip_id,
>>>>>>>> NPU_STCK2_CS_SM3_MISC_HIGH_WATER,
>>>>>>>> val,
>>>>>>>> + PPC_BITMASK(6,11));
>>>>>>>> /* Reassign the BARs */
>>>>>>>> assign_mmio_bars(npu->chip_id, npu->xscom_base, reg,
>>>>>>>> mm_win);
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>
>
--
Alexey
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