[Skiboot] [PATCH 4/4] hw/phb4: Drop FRESET_DEASSERT_DELAY state

[Oliver O'Halloran]

The delay between the ASSERT_DELAY and DEASSERT_DELAY states is set to
one timebase tick. This state seems to have been a hold over from PHB3
where it was used to add a 1s delay between de-asserting PERST and
polling the link for the CAPI FPGA. There's no requirement for that here
since the link polling on PHB4 is a bit smarter so we should be fine.

Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
---
 hw/phb4.c      | 5 -----
 include/phb4.h | 1 -
 2 files changed, 6 deletions(-)

diff --git a/hw/phb4.c b/hw/phb4.c
index 770c11efb99c..65288cfd3072 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -2999,11 +2999,6 @@ static int64_t phb4_freset(struct pci_slot *slot)
 
 		PHBDBG(p, "FRESET: Deassert\n");
 		phb4_assert_perst(slot, false);
-		pci_slot_set_state(slot, PHB4_SLOT_FRESET_DEASSERT_DELAY);
-		return pci_slot_set_sm_timeout(slot, msecs_to_tb(1));
-
-	case PHB4_SLOT_FRESET_DEASSERT_DELAY:
-		PHBDBG(p, "FRESET: Starting training\n");
 
 		phb4_training_trace(p);
 
diff --git a/include/phb4.h b/include/phb4.h
index 605effecfba1..c52a840d99ca 100644
--- a/include/phb4.h
+++ b/include/phb4.h
@@ -125,7 +125,6 @@
 #define PHB4_SLOT_FRESET			PCI_SLOT_STATE_FRESET
 #define   PHB4_SLOT_FRESET_START		(PHB4_SLOT_FRESET + 1)
 #define   PHB4_SLOT_FRESET_ASSERT_DELAY		(PHB4_SLOT_FRESET + 2)
-#define   PHB4_SLOT_FRESET_DEASSERT_DELAY	(PHB4_SLOT_FRESET + 3)
 #define PHB4_SLOT_CRESET			PCI_SLOT_STATE_CRESET
 #define   PHB4_SLOT_CRESET_START		(PHB4_SLOT_CRESET + 1)
 #define   PHB4_SLOT_CRESET_WAIT_CQ		(PHB4_SLOT_CRESET + 2)
-- 
2.20.1