[Skiboot] [PATCH v2 3/9] xive: Set the fused core mode properly

[Michael Neuling]

From: Benjamin Herrenschmidt <benh at kernel.crashing.org>

Set or clear the fused core mode bit in the XIVE inits
properly. While HostBoot is supposed to do it, I prefer
not depending on it doing the right thing, since we already
configure that register ourselves anyway.

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey at neuling.org>
---
 hw/xive.c      | 4 ++++
 include/xive.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/hw/xive.c b/hw/xive.c
index c9f3f07dfb..4444b6497a 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -1733,6 +1733,10 @@ static bool xive_config_init(struct xive *x)
 	val |= PC_TCTXT_CFG_LGS_EN;
 	/* Disable pressure relief as we hijack the field in the VPs */
 	val &= ~PC_TCTXT_CFG_STORE_ACK;
+	if (this_cpu()->is_fused_core)
+		val |= PC_TCTXT_CFG_FUSE_CORE_EN;
+	else
+		val &= ~PC_TCTXT_CFG_FUSE_CORE_EN;
 	xive_regw(x, PC_TCTXT_CFG, val);
 	xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val);
 
diff --git a/include/xive.h b/include/xive.h
index acc696a43a..f4365efc00 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -86,6 +86,7 @@
 #define  PC_TCTXT_CFG_TARGET_EN		PPC_BIT(1)
 #define  PC_TCTXT_CFG_LGS_EN		PPC_BIT(2)
 #define  PC_TCTXT_CFG_STORE_ACK		PPC_BIT(3)
+#define  PC_TCTXT_CFG_FUSE_CORE_EN	PPC_BIT(4)
 #define  PC_TCTXT_CFG_HARD_CHIPID_BLK	PPC_BIT(8)
 #define  PC_TCTXT_CHIPID_OVERRIDE	PPC_BIT(9)
 #define  PC_TCTXT_CHIPID		PPC_BITMASK(12,15)
-- 
2.20.1