[Skiboot] [PATCH v2 1/7] npu2-opencapi: Rework ODL register access

Frederic Barrat fbarrat at linux.ibm.com
Wed Mar 13 07:35:09 AEDT 2019


ODL registers used to control the opencapi link state have an address
built on a base address and an offset for each brick which can be
computed instead of hard-coded individually for each brick.
Rework how we access the ODL registers, to avoid repeating switch
statements all over the place.

Signed-off-by: Frederic Barrat <fbarrat at linux.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan at au1.ibm.com>
Reviewed-by: Christophe Lombard <clombard at linux.vnet.ibm.com>
---

v2: no change

hw/npu2-hw-procedures.c |  17 +------
 hw/npu2-opencapi.c      | 109 ++++------------------------------------
 include/npu2-regs.h     |  30 ++++-------
 3 files changed, 21 insertions(+), 135 deletions(-)

diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
index 627a8428..a10ccb7c 100644
--- a/hw/npu2-hw-procedures.c
+++ b/hw/npu2-hw-procedures.c
@@ -981,22 +981,7 @@ void npu2_opencapi_bump_ui_lane(struct npu2_dev *dev)
 	uint64_t status_xscom;
 	int lane, bit = 7;
 
-	switch (dev->brick_index) {
-	case 2:
-		status_xscom = OB0_ODL0_TRAINING_STATUS;
-		break;
-	case 3:
-		status_xscom = OB0_ODL1_TRAINING_STATUS;
-		break;
-	case 4:
-		status_xscom = OB3_ODL1_TRAINING_STATUS;
-		break;
-	case 5:
-		status_xscom = OB3_ODL0_TRAINING_STATUS;
-		break;
-	default:
-		assert(false);
-	}
+	status_xscom = OB_ODL_TRAINING_STATUS(dev->brick_index);
 	xscom_read(dev->npu->chip_id, status_xscom, &reg);
 	reg = GETFIELD(OB_ODL_TRAINING_STATUS_STS_RX_PATTERN_B, reg);
 
diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c
index aa3c434e..6ad561c4 100644
--- a/hw/npu2-opencapi.c
+++ b/hw/npu2-opencapi.c
@@ -128,24 +128,11 @@ static inline uint64_t index_to_block(uint64_t index) {
 	}
 }
 
-static uint64_t get_odl_status(uint32_t gcid, uint64_t index) {
+static uint64_t get_odl_status(uint32_t gcid, uint64_t index)
+{
 	uint64_t reg, status_xscom;
-	switch (index) {
-	case 2:
-		status_xscom = OB0_ODL0_STATUS;
-		break;
-	case 3:
-		status_xscom = OB0_ODL1_STATUS;
-		break;
-	case 4:
-		status_xscom = OB3_ODL1_STATUS;
-		break;
-	case 5:
-		status_xscom = OB3_ODL0_STATUS;
-		break;
-	default:
-		assert(false);
-	}
+
+	status_xscom = OB_ODL_STATUS(index);
 	xscom_read(gcid, status_xscom, &reg);
 	return reg;
 }
@@ -154,22 +141,7 @@ static uint64_t get_odl_training_status(uint32_t gcid, uint64_t index)
 {
 	uint64_t status_xscom, reg;
 
-	switch (index) {
-	case 2:
-		status_xscom = OB0_ODL0_TRAINING_STATUS;
-		break;
-	case 3:
-		status_xscom = OB0_ODL1_TRAINING_STATUS;
-		break;
-	case 4:
-		status_xscom = OB3_ODL1_TRAINING_STATUS;
-		break;
-	case 5:
-		status_xscom = OB3_ODL0_TRAINING_STATUS;
-		break;
-	default:
-		assert(false);
-	}
+	status_xscom = OB_ODL_TRAINING_STATUS(index);
 	xscom_read(gcid, status_xscom, &reg);
 	return reg;
 }
@@ -178,22 +150,7 @@ static uint64_t get_odl_endpoint_info(uint32_t gcid, uint64_t index)
 {
 	uint64_t status_xscom, reg;
 
-	switch (index) {
-	case 2:
-		status_xscom = OB0_ODL0_ENDPOINT_INFO;
-		break;
-	case 3:
-		status_xscom = OB0_ODL1_ENDPOINT_INFO;
-		break;
-	case 4:
-		status_xscom = OB3_ODL1_ENDPOINT_INFO;
-		break;
-	case 5:
-		status_xscom = OB3_ODL0_ENDPOINT_INFO;
-		break;
-	default:
-		assert(false);
-	}
+	status_xscom = OB_ODL_ENDPOINT_INFO(index);
 	xscom_read(gcid, status_xscom, &reg);
 	return reg;
 }
@@ -936,23 +893,7 @@ static void reset_odl(uint32_t gcid, struct npu2_dev *dev)
 {
 	uint64_t reg, config_xscom;
 
-	switch (dev->brick_index) {
-	case 2:
-		config_xscom = OB0_ODL0_CONFIG;
-		break;
-	case 3:
-		config_xscom = OB0_ODL1_CONFIG;
-		break;
-	case 4:
-		config_xscom = OB3_ODL1_CONFIG;
-		break;
-	case 5:
-		config_xscom = OB3_ODL0_CONFIG;
-		break;
-	default:
-		assert(false);
-	}
-
+	config_xscom = OB_ODL_CONFIG(dev->brick_index);
 	/* Reset ODL */
 	reg = OB_ODL_CONFIG_RESET;
 	reg = SETFIELD(OB_ODL_CONFIG_VERSION, reg, 0b000001);
@@ -972,23 +913,7 @@ static void set_init_pattern(uint32_t gcid, struct npu2_dev *dev)
 {
 	uint64_t reg, config_xscom;
 
-	switch (dev->brick_index) {
-	case 2:
-		config_xscom = OB0_ODL0_CONFIG;
-		break;
-	case 3:
-		config_xscom = OB0_ODL1_CONFIG;
-		break;
-	case 4:
-		config_xscom = OB3_ODL1_CONFIG;
-		break;
-	case 5:
-		config_xscom = OB3_ODL0_CONFIG;
-		break;
-	default:
-		assert(false);
-	}
-
+	config_xscom = OB_ODL_CONFIG(dev->brick_index);
 	/* Transmit Pattern A */
 	xscom_read(gcid, config_xscom, &reg);
 	reg = SETFIELD(OB_ODL_CONFIG_TRAIN_MODE, reg, 0b0001);
@@ -999,23 +924,7 @@ static void start_training(uint32_t gcid, struct npu2_dev *dev)
 {
 	uint64_t reg, config_xscom;
 
-	switch (dev->brick_index) {
-	case 2:
-		config_xscom = OB0_ODL0_CONFIG;
-		break;
-	case 3:
-		config_xscom = OB0_ODL1_CONFIG;
-		break;
-	case 4:
-		config_xscom = OB3_ODL1_CONFIG;
-		break;
-	case 5:
-		config_xscom = OB3_ODL0_CONFIG;
-		break;
-	default:
-		assert(false);
-	}
-
+	config_xscom = OB_ODL_CONFIG(dev->brick_index);
 	/* Start training */
 	xscom_read(gcid, config_xscom, &reg);
 	reg = SETFIELD(OB_ODL_CONFIG_TRAIN_MODE, reg, 0b1000);
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index 38087aab..5190aeb7 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -725,10 +725,11 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
 #define    PU_IOE_PB_FP_CFG_FP1_FMR_DISABLE	PPC_BIT(52)
 #define    PU_IOE_PB_FP_CFG_FP1_PRS_DISABLE	PPC_BIT(57)
 
-#define OB0_ODL0_CONFIG				0x901082A
-#define OB0_ODL1_CONFIG				0x901082B
-#define OB3_ODL0_CONFIG				0xC01082A
-#define OB3_ODL1_CONFIG				0xC01082B
+#define OB_ODL_OFFSET(brick_index) \
+	((((brick_index - 2) >> 1) * 0x3000000) + ((brick_index == 3 || brick_index == 4) ? 1 : 0))
+
+#define OB_ODL_CONFIG(brick_index) \
+	(0x901082A + OB_ODL_OFFSET(brick_index))
 #define   OB_ODL_CONFIG_RESET			PPC_BIT(0)
 #define   OB_ODL_CONFIG_VERSION			PPC_BITMASK(2, 7)
 #define   OB_ODL_CONFIG_TRAIN_MODE		PPC_BITMASK(8, 11)
@@ -737,26 +738,17 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
 #define   OB_ODL_CONFIG_PHY_CNTR_LIMIT		PPC_BITMASK(20, 23)
 #define   OB_ODL_CONFIG_DEBUG_ENABLE		PPC_BIT(33)
 #define   OB_ODL_CONFIG_FWD_PROGRESS_TIMER	PPC_BITMASK(40, 43)
-
-#define OB0_ODL0_STATUS				0x901082C
-#define OB0_ODL1_STATUS				0x901082D
-#define OB3_ODL0_STATUS				0xC01082C
-#define OB3_ODL1_STATUS				0xC01082D
+#define OB_ODL_STATUS(brick_index) \
+	(0x901082C + OB_ODL_OFFSET(brick_index))
 #define   OB_ODL_STATUS_TRAINED_MODE		PPC_BITMASK(0,3)
 #define   OB_ODL_STATUS_RX_TRAINED_LANES	PPC_BITMASK(16, 23)
 #define   OB_ODL_STATUS_TX_TRAINED_LANES	PPC_BITMASK(24, 31)
 #define   OB_ODL_STATUS_TRAINING_STATE_MACHINE	PPC_BITMASK(49, 51)
-
-#define OB0_ODL0_TRAINING_STATUS		0x901082E
-#define OB0_ODL1_TRAINING_STATUS		0x901082F
-#define OB3_ODL0_TRAINING_STATUS		0xC01082E
-#define OB3_ODL1_TRAINING_STATUS		0xC01082F
+#define OB_ODL_TRAINING_STATUS(brick_index) \
+	(0x901082E + OB_ODL_OFFSET(brick_index))
 #define   OB_ODL_TRAINING_STATUS_STS_RX_PATTERN_B PPC_BITMASK(8, 15)
-
-#define OB0_ODL0_ENDPOINT_INFO			0x9010832
-#define OB0_ODL1_ENDPOINT_INFO			0x9010833
-#define OB3_ODL0_ENDPOINT_INFO			0xC010832
-#define OB3_ODL1_ENDPOINT_INFO			0xC010833
+#define OB_ODL_ENDPOINT_INFO(brick_index)		\
+	(0x9010832 + OB_ODL_OFFSET(brick_index))
 
 /* Registers and bits used to clear the L2 and L3 cache */
 #define L2_PRD_PURGE_CMD_REG 			0x1080E
-- 
2.19.1



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