[Skiboot] [PATCH] hw/phb4: Squash the IO bridge window

[Oliver O'Halloran]

The PCI-PCI bridge spec says that bridges that implement an IO window
should hardcode the IO base and limit registers to zero.
Unfortunately, these registers only define the upper bits of the IO
window and the low bits are assumed to be 0 for the base and 1 for the
limit address. As a result, setting both to zero can be mis-interpreted
as a 4K IO window.

This patch fixes the problem the same way PHB3 does. It sets the IO base
and limit values to 0xf000 and 0x1000 respectively which most software
interprets as a disabled window.

lspci before patch:

0000:00:00.0 PCI bridge: IBM Device 04c1 (prog-if 00 [Normal decode])
	I/O behind bridge: 00000000-00000fff

lspci after patch:

0000:00:00.0 PCI bridge: IBM Device 04c1 (prog-if 00 [Normal decode])
	I/O behind bridge: None

Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
---
 hw/phb4.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/hw/phb4.c b/hw/phb4.c
index ffdb01632fd2..4e77dd8e58e8 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -319,6 +319,14 @@ static int64_t phb4_rc_read(struct phb4 *p, uint32_t offset, uint8_t sz,
 				oval = in_le32(p->regs + PHB_RC_CONFIG_BASE + reg);
 		}
 	}
+
+	/* Apply any post-read fixups */
+	switch (reg) {
+	case PCI_CFG_IO_BASE:
+		oval |= 0x01f1; /* Set IO base < limit to disable the window */
+		break;
+	}
+
 	switch (sz) {
 	case 1:
 		offset &= 3;
-- 
2.20.1