[Skiboot] [PATCH 6/7] hw: Introduce npu3

[christophe lombard]

On 12/06/2019 23:08, Reza Arbab wrote:
> POWER9P systems have been upgraded with NVLink 3.0 interconnects. The
> underlying hardware is fundamentally different--each POWER9 chip has
> 
>          (1 NPU) * (3 stacks) * (2 bricks) = (6 links)
> 
> Where in each POWER9P chip, there are
> 
>          (3 NPUs) * (4 bricks) = (12 links)
> 
> This flatter hierarchy simplifies the firmware implementation a bit, but
> also prevents sharing much common code with npu2.
> 
> As in previous versions, initialize the hardware and expose each link to
> the OS as a virtual PCIe device. This initial support covers NVLink
> devices only, with OpenCAPI to follow.
> 
> Signed-off-by: Reza Arbab <arbab at linux.ibm.com>

Our development on opencapi4 is based on Reza's patches and essentially 
this one.
Basic verification have also be done in Simics.
Thanks

Reviewed-by: Christophe Lombard <clombard at linux.vnet.ibm.com>