[Skiboot] [PATCH] doc: Futher document OPAL_REINIT_CPUS_MMU_* modes

Stewart Smith stewart at linux.ibm.com
Wed Jun 5 11:35:13 AEST 2019

Fixes: https://github.com/open-power/skiboot/issues/134
Signed-off-by: Stewart Smith <stewart at linux.ibm.com>
 doc/opal-api/opal-reinit-cpus-70.rst | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/doc/opal-api/opal-reinit-cpus-70.rst b/doc/opal-api/opal-reinit-cpus-70.rst
index 2522e76abe21..3a6e543738d3 100644
--- a/doc/opal-api/opal-reinit-cpus-70.rst
+++ b/doc/opal-api/opal-reinit-cpus-70.rst
 This flag requests that CPUs be configured with TM (Transactional Memory)
 suspend mode disabled. This may only be supported on some CPU versions.
+Some processors may need to change a processor specific register in order to
+support Hash or Radix translation.
+For POWER9 CPUs, this is bit 8 of the HID register (see the POWER9 User Manual
+for details). On POWER9 CPUS, when in Hash mode, the full TLB is available to
+the host OS rather than when in radix mode, half the TLB is taken for a Page
+Walk Cache (PWC).
+Future CPUs may or may not do anything with these flags, but a host OS must
+use them to ensure compatibility in the future.

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