[Skiboot] [PATCH] Allow to create slot for downstream port of any switch
oohall at gmail.com
Wed Jun 5 10:11:23 AEST 2019
On Tue, Jun 4, 2019 at 10:58 PM Ilya Kuznetsov <ilya at yadro.com> wrote:
> System vendor may build systems with large PCIe tree with
> deeper switch topologies. Currenlty downstream ports slot
> creation is limited to one switch. Patch allows to use more
> by removing comparison to third parent.
> Signed-off-by: Ilya Kuznetsov <ilya at yadro.com>
> core/pcie-slot.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
> diff --git a/core/pcie-slot.c b/core/pcie-slot.c
> index e7013d1e..b12e0fb2 100644
> --- a/core/pcie-slot.c
> +++ b/core/pcie-slot.c
> @@ -544,13 +544,9 @@ struct pci_slot *pcie_slot_create_dynamic(struct phb *phb,
> if (!phb || !pd || pd->slot)
> return NULL;
> - /* Try to create slot whose details aren't provided by platform.
> - * We only care the downstream ports of PCIe switch that connects
> - * to root port.
> - */
> + /* Try to create slot whose details aren't provided by platform. */
> if (pd->dev_type != PCIE_TYPE_SWITCH_DNPORT ||
> - !pd->parent || !pd->parent->parent ||
> - pd->parent->parent->parent)
> + !pd->parent || !pd->parent->parent)
> return NULL;
I'm not entirely sure why it had that restriction in the first place.
We could probably just limit the check to:
if (pd->dev_type != PCIE_TYPE_SWITCH_DNPORT)
The same function verifies the port has hotplug support advertised, so
there's no real harm in allowing it.
> ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
> Skiboot mailing list
> Skiboot at lists.ozlabs.org
More information about the Skiboot