[Skiboot] [RFC PATCH] Remove POWER9 DD1 support
Cédric Le Goater
clg at kaod.org
Tue Jan 15 18:08:55 AEDT 2019
>> diff --git a/hw/xive.c b/hw/xive.c
>> index 515f154d7..810538725 100644
>> --- a/hw/xive.c
>> +++ b/hw/xive.c
>> @@ -487,8 +487,7 @@ struct xive {
>> void *q_ovf;
>> };
>>
>> -#define XIVE_CAN_STORE_EOI(x) \
>> - (XIVE_STORE_EOI_ENABLED && ((x)->rev >= XIVE_REV_2))
>> +#define XIVE_CAN_STORE_EOI(x) XIVE_STORE_EOI_ENABLED
>
> OK. Let's keep the macro. P10 should have Store EOI.
>
>> /* Global DT node */
>> static struct dt_node *xive_dt_node;
>> @@ -1521,7 +1520,7 @@ static bool xive_set_vsd(struct xive *x, uint32_t tbl, uint32_t idx, uint64_t v)
>> SETFIELD(VST_TABLE_OFFSET, 0ull, idx));
>> if (x->last_reg_error)
>> return false;
>> - /* Hack to workaround DD1 issue with NVT in VC in DD1 */
>> + /* Hack to workaround DD1 issue with NVT in VC in DD1 XXX still needed? */
>> if (tbl == VST_TSEL_VPDT)
>> xive_regw(x, VC_VSD_TABLE_DATA, v | VSD_TSIZE);
>
> Yes. I will check. It has been a pain to model in QEMU.
All seems to work well without this hack on a DD2.1.
C.
>> else
>> @@ -1743,10 +1742,6 @@ static bool xive_config_init(struct xive *x)
>
>
> There is a check on XIVE_REV_2 that we could clean up :
>
> if (x->rev >= XIVE_REV_2) {
> val = SETFIELD(PC_TCTXT_INIT_AGE, val, 0x2);
> val |= PC_TCTXT_CFG_LGS_EN;
> /* Disable pressure relief as we hijack the field in the VPs */
> val &= ~PC_TCTXT_CFG_STORE_ACK;
> }
>
> I think.
>
>> xive_regw(x, PC_TCTXT_CFG, val);
>> xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val);
>>
>> - /* Subsequent inits are DD2 only */
>> - if (x->rev < XIVE_REV_2)
>> - return true;
>> -
>> val = xive_regr(x, CQ_CFG_PB_GEN);
>> /* 1-block-per-chip mode */
>> val = SETFIELD(CQ_INT_ADDR_OPT, val, 2);
>> @@ -2008,8 +2003,7 @@ static void xive_create_mmio_dt_node(struct xive *x)
>> 12, 16, 21, 24);
>>
>> dt_add_property_cells(xive_dt_node, "ibm,xive-#priorities", 8);
>> - if (x->rev >= XIVE_REV_2)
>> - dt_add_property(xive_dt_node, "single-escalation-support", NULL, 0);
>> + dt_add_property(xive_dt_node, "single-escalation-support", NULL, 0);
>>
>> xive_add_provisioning_properties();
>> }
>> @@ -2840,10 +2834,8 @@ static struct xive *init_one_xive(struct dt_node *np)
>>
>> x->rev = XIVE_REV_UNKNOWN;
>> if (chip->type == PROC_CHIP_P9_NIMBUS) {
>> - if ((chip->ec_level & 0xf0) == 0x10)
>> - x->rev = XIVE_REV_1;
>> - else if ((chip->ec_level & 0xf0) == 0x20)
>> - x->rev = XIVE_REV_2;
>> + assert((chip->ec_level & 0xf0) != 0x10);
>> + x->rev = XIVE_REV_2;
>> } else if (chip->type == PROC_CHIP_P9_CUMULUS)
>> x->rev = XIVE_REV_2;
>
> So all P9s are XIVE_REV_2 now ?
>
> C.
>
>
>> @@ -4399,16 +4391,9 @@ static int64_t opal_xive_set_vp_info(uint64_t vp_id,
>> vp_new.w6 = report_cl_pair >> 32;
>> vp_new.w7 = report_cl_pair & 0xffffffff;
>>
>> - if (flags & OPAL_XIVE_VP_SINGLE_ESCALATION) {
>> - if (x->rev < XIVE_REV_2) {
>> - xive_dbg(x, "Attempt at enabling single escalate"
>> - " on xive rev %d failed\n",
>> - x->rev);
>> - unlock(&x->lock);
>> - return OPAL_PARAMETER;
>> - }
>> + if (flags & OPAL_XIVE_VP_SINGLE_ESCALATION)
>> rc = xive_setup_silent_gather(vp_id, true);
>> - } else
>> + else
>> rc = xive_setup_silent_gather(vp_id, false);
>> } else {
>> vp_new.w0 = vp_new.w6 = vp_new.w7 = 0;
>> diff --git a/include/lpc.h b/include/lpc.h
>> index 19bf47910..83b6c9dbe 100644
>> --- a/include/lpc.h
>> +++ b/include/lpc.h
>> @@ -100,9 +100,6 @@ extern void lpc_register_client(uint32_t chip_id, const struct lpc_client *clt,
>> /* Return the policy for a given serirq */
>> extern unsigned int lpc_get_irq_policy(uint32_t chip_id, uint32_t psi_idx);
>>
>> -/* Clear SerIRQ latch on P9 DD1 */
>> -extern void lpc_p9_sirq_eoi(uint32_t chip_id, uint32_t index);
>> -
>> /* Default bus accessors that perform error logging */
>> extern int64_t lpc_write(enum OpalLPCAddressType addr_type, uint32_t addr,
>> uint32_t data, uint32_t sz);
>> diff --git a/include/phb4-regs.h b/include/phb4-regs.h
>> index 235c213f9..8dd8cdc55 100644
>> --- a/include/phb4-regs.h
>> +++ b/include/phb4-regs.h
>> @@ -119,11 +119,6 @@
>> #define PHB_CTRLR_CFG_EEH_BLOCK PPC_BIT(15)
>> #define PHB_CTRLR_FENCE_LNKILL_DIS PPC_BIT(16)
>> #define PHB_CTRLR_TVT_ADDR_SEL PPC_BITMASK(17,19)
>> -#define TVT_DD1_1_PER_PE 0
>> -#define TVT_DD1_2_PER_PE 1
>> -#define TVT_DD1_4_PER_PE 2
>> -#define TVT_DD1_8_PER_PE 3
>> -#define TVT_DD1_16_PER_PE 4
>> #define TVT_2_PER_PE 0
>> #define TVT_4_PER_PE 1
>> #define TVT_8_PER_PE 2
>> @@ -308,8 +303,6 @@
>> #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8
>> #define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0
>> #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8
>> -#define PHB_PCIE_LANE_EQ_CNTL22 0x1B00 /* DD1 only */
>> -#define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */
>> #define PHB_PCIE_TRACE_CTRL 0x1B20
>> #define PHB_PCIE_MISC_STRAP 0x1B30
>>
>>
>
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