[Skiboot] [PATCH 07/16] core: hardcode P9 large decrementer width

[Nicholas Piggin]

There is no good reason to "discover" the large decremeter width.
We are firmware, we know the large decrementer width.

Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
---
 core/cpu.c | 43 +++++++------------------------------------
 1 file changed, 7 insertions(+), 36 deletions(-)

diff --git a/core/cpu.c b/core/cpu.c
index 5d933bf5c..e7ffe3003 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -1044,48 +1044,19 @@ void init_boot_cpu(void)
 	init_hid();
 }
 
-static void enable_large_dec(bool on)
-{
-	u64 lpcr = mfspr(SPR_LPCR);
-
-	if (on)
-		lpcr |= SPR_LPCR_P9_LD;
-	else
-		lpcr &= ~SPR_LPCR_P9_LD;
-
-	mtspr(SPR_LPCR, lpcr);
-	isync();
-}
-
-#define HIGH_BIT (1ull << 63)
-
 static int find_dec_bits(void)
 {
-	int bits = 65; /* we always decrement once */
-	u64 mask = ~0ull;
+	int bits;
 
 	if (proc_gen < proc_gen_p9)
-		return 32;
-
-	/* The ISA doesn't specify the width of the decrementer register so we
-	 * need to discover it. When in large mode (LPCR.LD = 1) reads from the
-	 * DEC SPR are sign extended to 64 bits and writes are truncated to the
-	 * physical register width. We can use this behaviour to detect the
-	 * width by starting from an all 1s value and left shifting until we
-	 * read a value from the DEC with it's high bit cleared.
-	 */
-
-	enable_large_dec(true);
-
-	do {
-		bits--;
-		mask = mask >> 1;
-		mtspr(SPR_DEC, mask);
-	} while (mfspr(SPR_DEC) & HIGH_BIT);
-
-	enable_large_dec(false);
+		bits = 32;
+	else if (proc_gen == proc_gen_p9)
+		bits = 56;
+	else
+		assert(0);
 
 	prlog(PR_DEBUG, "CPU: decrementer bits %d\n", bits);
+
 	return bits;
 }
 
-- 
2.18.0