[Skiboot] [PATCH 1/2] npu3: Rename NPU3_SM_MISC_CFGn register macros

[Reza Arbab]

The SM blocks have multiple MISC_CFG registers. For example, there are
both CS.SM0.MCP.MISC.CONFIG0 and CS.SM0.SNP.MISC.CONFIG0. Rename our
macro for the former to more clearly reflect this and avoid a clash when
the latter is added.

Signed-off-by: Reza Arbab <arbab at linux.ibm.com>
---
 hw/npu3.c           | 10 +++++-----
 include/npu3-regs.h | 14 +++++++-------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/hw/npu3.c b/hw/npu3.c
index e49e9bef2a96..ea687f43c5e7 100644
--- a/hw/npu3.c
+++ b/hw/npu3.c
@@ -301,12 +301,12 @@ static void npu3_misc_config(struct npu3 *npu)
 	npu3_for_each_nvlink_dev(dev, npu)
 		typemap |= 0x10 >> dev->index;
 
-	reg = NPU3_SM_MISC_CFG0;
+	reg = NPU3_MCP_MISC_CFG0;
 	val = npu3_read(npu, reg);
-	val |= NPU3_SM_MISC_CFG0_ENABLE_PBUS;
-	val &= ~NPU3_SM_MISC_CFG0_ENABLE_SNARF_CPM;
-	val = SETFIELD(NPU3_SM_MISC_CFG0_NVLINK_MODE, val, typemap);
-	val = SETFIELD(NPU3_SM_MISC_CFG0_OCAPI_MODE, val, ~typemap);
+	val |= NPU3_MCP_MISC_CFG0_ENABLE_PBUS;
+	val &= ~NPU3_MCP_MISC_CFG0_ENABLE_SNARF_CPM;
+	val = SETFIELD(NPU3_MCP_MISC_CFG0_NVLINK_MODE, val, typemap);
+	val = SETFIELD(NPU3_MCP_MISC_CFG0_OCAPI_MODE, val, ~typemap);
 	npu3_write(npu, reg, val);
 
 	reg = NPU3_CTL_MISC_CFG2;
diff --git a/include/npu3-regs.h b/include/npu3-regs.h
index 2e1dc3930574..c0c7eab0396d 100644
--- a/include/npu3-regs.h
+++ b/include/npu3-regs.h
@@ -86,13 +86,13 @@
  * Definitions here use NPU3_BLOCK_CQ_SM(0), but when npu3_write() is given
  * one of these, it will do corresponding writes to every CQ_SM block.
  */
-#define NPU3_SM_MISC_CFG0			(NPU3_BLOCK_CQ_SM(0) + 0x000)
-#define   NPU3_SM_MISC_CFG0_ENABLE_PBUS		PPC_BIT(26)
-#define   NPU3_SM_MISC_CFG0_ENABLE_SNARF_CPM	PPC_BIT(27)
-#define   NPU3_SM_MISC_CFG0_OCAPI_MODE		PPC_BITMASK(44, 48)
-#define   NPU3_SM_MISC_CFG0_NVLINK_MODE		PPC_BITMASK(49, 53)
-#define NPU3_SM_MISC_CFG1			(NPU3_BLOCK_CQ_SM(0) + 0x008)
-#define NPU3_SM_MISC_CFG2			(NPU3_BLOCK_CQ_SM(0) + 0x0f0)
+#define NPU3_MCP_MISC_CFG0			(NPU3_BLOCK_CQ_SM(0) + 0x000)
+#define   NPU3_MCP_MISC_CFG0_ENABLE_PBUS	PPC_BIT(26)
+#define   NPU3_MCP_MISC_CFG0_ENABLE_SNARF_CPM	PPC_BIT(27)
+#define   NPU3_MCP_MISC_CFG0_OCAPI_MODE		PPC_BITMASK(44, 48)
+#define   NPU3_MCP_MISC_CFG0_NVLINK_MODE	PPC_BITMASK(49, 53)
+#define NPU3_MCP_MISC_CFG1			(NPU3_BLOCK_CQ_SM(0) + 0x008)
+#define NPU3_MCP_MISC_CFG2			(NPU3_BLOCK_CQ_SM(0) + 0x0f0)
 #define NPU3_GPU_MEM_BAR(brk)			(NPU3_BLOCK_CQ_SM(0) + 0x190 + (brk) * 8)
 #define   NPU3_GPU_MEM_BAR_ENABLE		PPC_BIT(0)
 #define   NPU3_GPU_MEM_BAR_ADDR_MASK		PPC_BITMASK(1, 35)
-- 
1.8.3.1