[Skiboot] [RFC PATCH 15/23] hw/phb3: Convert to generic FRESET

[Frederic Barrat]

Le 03/04/2019 à 11:09, Oliver O'Halloran a écrit :
> NB: This removes the 1s wait after lifting PERST. This wait was added to
> allow some FPGA cards time to flash their bitstream since the PCIe
> interface would not be enabled until the image was flashed. We has since
> extended the time we spend waiting for an electrical link to 1s so this
> wait should not be necessary any longer.
> 
> Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
> ---
> Tested on p83 with an Altera FPGA card with a CAPI image. Seems to work
> just fine...
> ---
>   hw/phb3.c | 57 +------------------------------------------------------
>   1 file changed, 1 insertion(+), 56 deletions(-)
> 
> diff --git a/hw/phb3.c b/hw/phb3.c
> index 4ac6aa729c4d..d86fb74bbbf9 100644
> --- a/hw/phb3.c
> +++ b/hw/phb3.c
> @@ -2418,61 +2418,6 @@ static int64_t phb3_assert_perst(struct pci_slot *slot, bool assert)
>   	return OPAL_SUCCESS;
>   }
>   
> -static int64_t phb3_freset(struct pci_slot *slot)
> -{
> -	struct phb3 *p = phb_to_phb3(slot->phb);
> -	uint8_t presence = 1;
> -
> -	switch(slot->state) {
> -	case PHB3_SLOT_NORMAL:
> -		PHBDBG(p, "FRESET: Starts\n");
> -
> -		/* Nothing to do without adapter connected */
> -		if (slot->ops.get_presence_state)
> -			slot->ops.get_presence_state(slot, &presence);
> -		if (!presence) {
> -			PHBDBG(p, "FRESET: No device\n");
> -			return OPAL_SUCCESS;
> -		}

So we're losing presence detection with the generic freset. I haven't 
followed through exactly the consequences, hopefully we won't try to 
train the link (?)

   Fred


> -
> -		PHBDBG(p, "FRESET: Prepare for link down\n");
> -		slot->retry_state = PHB3_SLOT_FRESET_START;
> -		if (slot->ops.prepare_link_change)
> -			slot->ops.prepare_link_change(slot, false);
> -		/* fall through */
> -	case PHB3_SLOT_FRESET_START:
> -		if (!p->skip_perst) {
> -			PHBDBG(p, "FRESET: Assert\n");
> -			phb3_assert_perst(slot, true);
> -			pci_slot_set_state(slot,
> -				PHB3_SLOT_FRESET_ASSERT_DELAY);
> -			return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
> -		}
> -
> -		/* To skip the assert during boot time */
> -		PHBDBG(p, "FRESET: Assert skipped\n");
> -		pci_slot_set_state(slot, PHB3_SLOT_FRESET_ASSERT_DELAY);
> -		p->skip_perst = false;
> -		/* fall through */
> -	case PHB3_SLOT_FRESET_ASSERT_DELAY:
> -		PHBDBG(p, "FRESET: Deassert\n");
> -		phb3_assert_perst(slot, false);
> -		pci_slot_set_state(slot,
> -			PHB3_SLOT_FRESET_DEASSERT_DELAY);
> -
> -		/* CAPP FPGA requires 1s to flash before polling link */
> -		return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
> -	case PHB3_SLOT_FRESET_DEASSERT_DELAY:
> -		pci_slot_set_state(slot, PHB3_SLOT_LINK_START);
> -		return slot->ops.poll_link(slot);
> -	default:
> -		PHBERR(p, "Unexpected slot state %08x\n", slot->state);
> -	}
> -
> -	pci_slot_set_state(slot, PHB3_SLOT_NORMAL);
> -	return OPAL_HARDWARE;
> -}
> -
>   static int64_t load_capp_ucode(struct phb3 *p)
>   {
>   	int64_t rc;
> @@ -2753,7 +2698,7 @@ static struct pci_slot *phb3_slot_create(struct phb *phb)
>   	slot->ops.prepare_link_change	= phb3_prepare_link_change;
>   	slot->ops.poll_link		= phb3_poll_link;
>   	slot->ops.hreset		= phb3_hreset;
> -	slot->ops.freset		= phb3_freset;
> +	slot->ops.freset		= pci_slot_generic_freset;
>   	slot->ops.creset		= phb3_creset;
>   
>   	return slot;
>