[Skiboot] [RFC PATCH 02/23] core/pcie-slot: Make power control synchronous

[Oliver O'Halloran]

Hack in a synchronus wait rather than returning OPAL_ASYNC_TOKEN so the
the caller waits for the POWER_ON operation to finish. We want to
convert the existing users of the set_power_state() API to use a polling
based API rather than the crapshoot of async completion callbacks we
have now.

Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
---
 core/pcie-slot.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/core/pcie-slot.c b/core/pcie-slot.c
index ead767de01e4..0ed903501178 100644
--- a/core/pcie-slot.c
+++ b/core/pcie-slot.c
@@ -256,7 +256,6 @@ static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val,
 		 */
 	}
 
-	pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_START);
 	slot->power_state = val;
 	ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
 	pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state);
@@ -269,16 +268,20 @@ static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val,
 		state |= (PCIE_INDIC_ON << 8);
 		break;
 	default:
-		pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
 		prlog(PR_ERR, PCIE_SLOT_PREFIX
 		      "Invalid power state (0x%x)\n", slot->id, val);
 		return OPAL_PARAMETER;
 	}
 
 	pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, state);
-	pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_DONE);
 
-	return OPAL_ASYNC_COMPLETION;
+	/*
+	 * HACK: wait a bit for the link to come up. Drop this once we've
+	 * converted users of set_power_state to use the new interface
+	 */
+	time_wait_ms(10);
+
+	return OPAL_SUCCESS;
 }
 
 static int64_t pcie_slot_set_power_state(struct pci_slot *slot, uint8_t val)
-- 
2.20.1