[Skiboot] [PATCH 1/2] xscom-utils/getsram: Make it work on P9

[Oliver O'Halloran]

The XSCOM base address of the OCC control registers changed slightly
between P8 and P9. Fix this up and add a bit of PVR checking so we look
in the right place.

Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
---
 external/xscom-utils/sram.c | 81 ++++++++++++++++++++++++++++++++-------------
 1 file changed, 58 insertions(+), 23 deletions(-)

diff --git a/external/xscom-utils/sram.c b/external/xscom-utils/sram.c
index 721adee6569d..9332e20d9508 100644
--- a/external/xscom-utils/sram.c
+++ b/external/xscom-utils/sram.c
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <stdio.h>
 #include <stdbool.h>
+#include <stdlib.h>
 #include <time.h>
 
 #include "xscom.h"
@@ -24,45 +25,79 @@
 #define DBG(fmt...)	do { if (verbose) printf(fmt); } while(0)
 #define ERR(fmt...)	do { fprintf(stderr, fmt); } while(0)
 
-#define OCB_PIB_OCBCSR0_0x0006B011	0x0006B011
-#define OCB_PIB_OCBCSR0_ANDx0006B012	0x0006B012
-#define OCB_PIB_OCBCSR0_ORx0006B013	0x0006B013
+#define OCB_PIB_BASE_P8 0x0006B000
+#define OCB_PIB_BASE_P9 0x0006D000
+
+#define OCBCSR0         0x11
+#define OCBCSR0_AND     0x12
+#define OCBCSR0_OR      0x13
 #define   OCB_STREAM_MODE			PPC_BIT(4)
 #define   OCB_STREAM_TYPE			PPC_BIT(5)
-#define OCB_PIB_OCBAR0_0x0006B010	0x0006B010
-#define OCB_PIB_OCBDR0_0x0006B015	0x0006B015
+#define OCBAR0          0x10
+#define OCBDR0          0x15
+
+#define PVR_TYPE_P8E    0x004b /* Murano */
+#define PVR_TYPE_P8     0x004d /* Venice */
+#define PVR_TYPE_P8NVL  0x004c /* Naples */
+#define PVR_TYPE_P9     0x004e
+
+#ifdef __powerpc__
+static uint64_t get_xscom_base(void)
+{
+	unsigned int pvr;
+
+	asm volatile("mfpvr %0" : "=r" (pvr));
+
+	switch (pvr >> 16) {
+	case PVR_TYPE_P9:
+		return OCB_PIB_BASE_P9;
+
+	case PVR_TYPE_P8E:
+	case PVR_TYPE_P8:
+	case PVR_TYPE_P8NVL:
+		return OCB_PIB_BASE_P8;
+	}
+
+	ERR("Unknown processor, exiting\n");
+	exit(1);
+	return 0;
+}
+#else
+/* Just so it compiles on x86 */
+static uint64_t get_xscom_base(void) { return 0; }
+#endif
 
 int sram_read(uint32_t chip_id, int chan, uint32_t addr, uint64_t *val)
 {
+	uint64_t sdat, base = get_xscom_base();
 	uint32_t coff = chan * 0x20;
-	uint64_t sdat;
 	int rc;
 
 	/* Read for debug purposes */
-	rc = xscom_read(chip_id, OCB_PIB_OCBCSR0_0x0006B011 + coff, &sdat);
+	rc = xscom_read(chip_id, base + OCBCSR0 + coff, &sdat);
 	if (rc) {
-		ERR("xscom OCB_PIB_OCBCSR0_0x0006B011 read error %d\n", rc);
+		ERR("xscom OCBCSR0 read error %d\n", rc);
 		return -1;
 	}
 
 	/* Create an AND mask to clear bit 4 and 5 and poke the AND register */
 	sdat = ~(OCB_STREAM_MODE | OCB_STREAM_TYPE);
-	rc = xscom_write(chip_id, OCB_PIB_OCBCSR0_ANDx0006B012 + coff, sdat);
+	rc = xscom_write(chip_id, base + OCBCSR0_AND + coff, sdat);
 	if (rc) {
-		ERR("xscom OCB_PIB_OCBCSR0_ANDx0006B012 write error %d\n", rc);
+		ERR("xscom OCBCSR0_AND write error %d\n", rc);
 		return -1;
 	}
 
 	sdat = ((uint64_t)addr) << 32;
-	rc = xscom_write(chip_id, OCB_PIB_OCBAR0_0x0006B010 + coff, sdat);
+	rc = xscom_write(chip_id, base + OCBAR0 + coff, sdat);
 	if (rc) {
-		ERR("xscom OCB_PIB_OCBAR0_0x0006B010 write error %d\n", rc);
+		ERR("xscom OCBAR0 write error %d\n", rc);
 		return -1;
 	}
 
-	rc = xscom_read(chip_id, OCB_PIB_OCBDR0_0x0006B015 + coff, val);
+	rc = xscom_read(chip_id, base + OCBDR0 + coff, val);
 	if (rc) {
-		ERR("xscom OCB_PIB_OCBAR0_0x0006B010 read error %d\n", rc);
+		ERR("xscom OCBDR0 read error %d\n", rc);
 		return -1;
 	}
 	return 0;
@@ -70,8 +105,8 @@ int sram_read(uint32_t chip_id, int chan, uint32_t addr, uint64_t *val)
 
 int sram_write(uint32_t chip_id, int chan, uint32_t addr, uint64_t val)
 {
+	uint64_t sdat, base = get_xscom_base();
 	uint32_t coff = chan * 0x20;
-	uint64_t sdat;
 	int rc;
 
 #if 0
@@ -83,30 +118,30 @@ int sram_write(uint32_t chip_id, int chan, uint32_t addr, uint64_t val)
 #endif
 
 	/* Read for debug purposes */
-	rc = xscom_read(chip_id, OCB_PIB_OCBCSR0_0x0006B011 + coff, &sdat);
+	rc = xscom_read(chip_id, base + OCBCSR0 + coff, &sdat);
 	if (rc) {
-		ERR("xscom OCB_PIB_OCBCSR0_0x0006B011 read error %d\n", rc);
+		ERR("xscom OCBCSR0 read error %d\n", rc);
 		return -1;
 	}
 
 	/* Create an AND mask to clear bit 4 and 5 and poke the AND register */
 	sdat = ~(OCB_STREAM_MODE | OCB_STREAM_TYPE);
-	rc = xscom_write(chip_id, OCB_PIB_OCBCSR0_ANDx0006B012 + coff, sdat);
+	rc = xscom_write(chip_id, base + OCBCSR0_AND + coff, sdat);
 	if (rc) {
-		ERR("xscom OCB_PIB_OCBCSR0_ANDx0006B012 write error %d\n", rc);
+		ERR("xscom OCBCSR0_AND write error %d\n", rc);
 		return -1;
 	}
 
 	sdat = ((uint64_t)addr) << 32;
-	rc = xscom_write(chip_id, OCB_PIB_OCBAR0_0x0006B010 + coff, sdat);
+	rc = xscom_write(chip_id, base + OCBAR0 + coff, sdat);
 	if (rc) {
-		ERR("xscom OCB_PIB_OCBAR0_0x0006B010 write error %d\n", rc);
+		ERR("xscom OCBAR0 write error %d\n", rc);
 		return -1;
 	}
 
-	rc = xscom_write(chip_id, OCB_PIB_OCBDR0_0x0006B015 + coff, val);
+	rc = xscom_write(chip_id, base + OCBDR0 + coff, val);
 	if (rc) {
-		ERR("xscom OCB_PIB_OCBAR0_0x0006B010 write error %d\n", rc);
+		ERR("xscom OCBDR0 write error %d\n", rc);
 		return -1;
 	}
 	return 0;
-- 
2.9.5