[Skiboot] [PATCH] lpc: Clear sync no-response field prior to device probe

[Joel Stanley]

On Thu, 18 Oct 2018 at 18:29, Andrew Jeffery <andrew at aj.id.au> wrote:
>
> Artem Senichev reported[1] his P8 platform was failing to boot from
> a43e9a66aae9 ("astbmc: Fail SFC init if SIO is unavailable") with the
> following error:
>
> [  110.097168975,3] PLAT: Failed to open PNOR flash controller

Yep, this bricked my Garrison:

[  118.463273159,3] PLAT: Failed to open PNOR flash controller
[  119.309908447,2] NVRAM: Failed to load
[  119.309999680,2] NVRAM: Failed to load
[  119.311393404,2] NVRAM: Failed to load
[  119.312534959,2] NVRAM: Failed to load
[  119.312612048,2] NVRAM: Failed to load

With your patch it looked okay. I did see this on the next boot:

[  138.038277373,7] OPAL: Start CPU 0x00ee (PIR 0x00ee) -> 0x000000000000a96c
[  138.047297723,7] OPAL: Start CPU 0x00ef (PIR 0x00ef) -> 0x000000000000a96c
[  138.097362833,3] LPC[000]: Got SYNC no-response error. Error
address reg: 0xd001002f
[  138.097391393,6] IPMI: dropping non severe PEL event
[  138.100886198,7] UART: IRQ functional !
[  138.100939322,7] PHB#0009: Got interrupt 0x000057ff
[  138.112595579,7] IPMI Get Message Flags: 02
[  138.112995295,7] IPMI Get Message Flags: 02
[  138.113537667,7] IPMI read event 35 complete: 16 bytes. cc: 00
[  138.113542495,6] IPMI: dropping System Event Record SEL
[  138.113998903,7] IPMI: Got error response 0x80

>
> I reproduced this behaviour on a Palmetto; we need to ensure the state
> of the no-response error bit is clear before proceding with the presence
> test.
>
> The fix appears to resolve the failure to open the PNOR flash controller
> on Palmetto and doesn't change the expected behaviour on Witherspoon.
>
> [1] https://github.com/open-power/skiboot/issues/197
>
> Signed-off-by: Andrew Jeffery <andrew at aj.id.au>

Tested-by: Joel Stanley <joel at jms.id.au>