[Skiboot] [PATCH] capi: Add a comment for the Transport Control Register

[Christophe Lombard]

The transport control register needs to be loaded in two steps: Once
the register values have been set, we have to write bit 63 to a '1',
which loads the register values into the ci store buffer logic.
Bit 63 always reads back as a zero but to load the ci store buffer
values in capp the transition of 0 to 1 of bit 63 must be seen.

A new comment is added in the code to avoid confusion and to precise
the feature of this register.

Signed-off-by: Christophe Lombard <clombard at linux.vnet.ibm.com>
---
 hw/phb4.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/phb4.c b/hw/phb4.c
index 18e1e0f..ae584d6 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -3764,7 +3764,11 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 	}
 	xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);
 
-	/* Initialize CI Store Buffers */
+	/* The transport control register needs to be loaded in two
+	 * steps. Once the register values have been set, we have to
+	 * write bit 63 to a '1', which loads the register values into
+	 * the ci store buffer logic.
+	 */
 	xscom_read(p->chip_id, TRANSPORT_CONTROL + offset, &reg);
 	reg |= PPC_BIT(63);
 	xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);
-- 
2.7.4