[Skiboot] [PATCH v2] phb4: Hardware init updates

Russell Currey ruscur at russell.cc
Tue May 1 14:24:55 AEST 2018


CFG Write Request Timeout was incorrectly set to informational and not
fatal for both non-CAPI and CAPI, so set it to fatal.  This was a
mistake in the specification.  Correcting this fixes a niche bug in
escalation (which is necessary on pre-DD2.2) that can cause a checkstop
due to a NCU timeout.

In addition, set the values in the timeout control registers to match.
This fixes an extremely rare and unreproducible bug, though the current
timings don't make sense since they're higher than the NCU timeout (16)
which will checkstop the machine anyway.

Signed-off-by: Russell Currey <ruscur at russell.cc>
---
Since v1: Added bit for CAPI too, added timer change

 hw/phb4.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/phb4.c b/hw/phb4.c
index 50e1be1c..f153ad02 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -3816,7 +3816,7 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 static void phb4_init_capp_errors(struct phb4 *p)
 {
 	/* Init_77: TXE Error AIB Fence Enable Register */
-	out_be64(p->regs + 0x0d30,	0xdff7bf0bf7ddfff0ull);
+	out_be64(p->regs + 0x0d30,	0xdff7bf0ff7ddfff0ull);
 
 	/* Init_86: RXE_ARB Error AIB Fence Enable Register */
 	out_be64(p->regs + 0x0db0,	0xfbffd7bbfb7fbfefull);
@@ -4463,7 +4463,7 @@ static void phb4_init_errors(struct phb4 *p)
 	out_be64(p->regs + 0x0d08,	0x0000000000000000ull);
 	out_be64(p->regs + 0x0d18,	0xffffff0fffffffffull);
 	out_be64(p->regs + 0x0d28,	0x0000400a00000000ull);
-	out_be64(p->regs + 0x0d30,	0xdff7bd01f7ddfff0ull); /* XXX CAPI has diff. value */
+	out_be64(p->regs + 0x0d30,	0xdff7bd05f7ddfff0ull); /* XXX CAPI has diff. value */
 	out_be64(p->regs + 0x0d40,	0x0000000000000000ull);
 	out_be64(p->regs + 0x0d48,	0x0000000000000000ull);
 	out_be64(p->regs + 0x0d50,	0x0000000000000000ull);
@@ -4722,7 +4722,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
 	out_be64(p->regs + PHB_TIMEOUT_CTRL1,			0x0015150000150000ull);
 
 	/* Init_134 - Timeout Control Register 2 */
-	out_be64(p->regs + PHB_TIMEOUT_CTRL2,			0x0000181700000000ull);
+	out_be64(p->regs + PHB_TIMEOUT_CTRL2,			0x0000151500000000ull);
 
 	/* Init_135 - PBL Timeout Control Register */
 	out_be64(p->regs + PHB_PBL_TIMEOUT_CTRL,		0x2013000000000000ull);
-- 
2.14.1



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