[Skiboot] [PATCH 1/2] npu2/hw-procedures: Don't open code NPU2_NTL_MISC_CFG2_BRICK_ENABLE
Reza Arbab
arbab at linux.ibm.com
Sat Jul 14 07:02:42 AEST 2018
Name this bit properly. There's a lot more cleanup like this to be done,
but I'm catching this one now as part of some related changes.
Signed-off-by: Reza Arbab <arbab at linux.ibm.com>
---
hw/npu2.c | 13 +++++++------
include/npu2-regs.h | 1 +
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/npu2.c b/hw/npu2.c
index 8e2f6fe..231bd6e 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -1404,12 +1404,13 @@ static void npu2_probe_phb(struct dt_node *dn)
xscom_write_mask(gcid, 0x50112f1, PPC_BIT(41), PPC_BIT(41));
xscom_write_mask(gcid, 0x50114f1, PPC_BIT(41), PPC_BIT(41));
- xscom_write_mask(gcid, 0x5011110, PPC_BIT(0), PPC_BIT(0));
- xscom_write_mask(gcid, 0x5011130, PPC_BIT(0), PPC_BIT(0));
- xscom_write_mask(gcid, 0x5011310, PPC_BIT(0), PPC_BIT(0));
- xscom_write_mask(gcid, 0x5011330, PPC_BIT(0), PPC_BIT(0));
- xscom_write_mask(gcid, 0x5011510, PPC_BIT(0), PPC_BIT(0));
- xscom_write_mask(gcid, 0x5011530, PPC_BIT(0), PPC_BIT(0));
+ val = NPU2_NTL_MISC_CFG2_BRICK_ENABLE;
+ xscom_write_mask(gcid, 0x5011110, val, val);
+ xscom_write_mask(gcid, 0x5011130, val, val);
+ xscom_write_mask(gcid, 0x5011310, val, val);
+ xscom_write_mask(gcid, 0x5011330, val, val);
+ xscom_write_mask(gcid, 0x5011510, val, val);
+ xscom_write_mask(gcid, 0x5011530, val, val);
/*
* Enable relaxed ordering for peer-to-peer reads
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index a8f571e..f67af97 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -268,6 +268,7 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
/* NTL block registers */
#define NPU2_NTL_MISC_CFG2(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x000)
+#define NPU2_NTL_MISC_CFG2_BRICK_ENABLE PPC_BIT(0)
#define NPU2_NTL_MISC_CFG3(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x008)
#define NPU2_NTL_ERR_HOLD1(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x010)
#define NPU2_NTL_ERR_MASK1(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x018)
--
1.8.3.1
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