[Skiboot] [PATCH v6 1/2] phb4: set PHB CMPM registers for tunneled operations

[Philippe Bergheaud]

P9 supports PCI tunneled operations (atomics and as_notify) that require
setting the PHB ASN Compare/Mask register with a 16-bit indication.

This register is currently initialized by enable_capi_mode(). But, as
tunneled operations may also work in PCI mode, the ASN Compare/Mask
register should rather be initialized in phb4_init_ioda3().

This patch also adds "ibm,phb-indications" to the device tree, to tell
Linux the values of CAPI, ASN, and NBW indications, when supported.

Tunneled operations tested by IBM in CAPI mode, by Mellanox Technologies
in PCI mode.

Signed-off-by: Philippe Bergheaud <felix at linux.vnet.ibm.com>
---
Changelog:

v2: Do not let Linux choose indication values.
    Let skiboot tell Linux via the device tree.
    Initialize the PHB ASN indication in PCI mode.

v3: No functional change.
    Drop cosmetic fixes in comments.

v4: No change.

v5: Set bit 59 of ASN indication and mask, as required for as_notify,
    in order to prevent address translation on lpid,pid,tid messages,
    that are not real addresses.

v6: No change.
---
 hw/phb4.c           | 28 +++++++++++++++++++++-------
 include/phb4-regs.h |  4 ++--
 2 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/hw/phb4.c b/hw/phb4.c
index 9748a1b7..83ee6de8 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -3724,6 +3724,13 @@ static void phb4_init_capp_errors(struct phb4 *p)
 	out_be64(p->regs + 0x0cb0,	0x35777073ff000000ull);
 }
 
+#define CAPIIND		0x0200
+#define CAPIMASK	0xFE00
+#define ASNIND		0x0C00
+#define ASNMASK		0xFFFF
+#define NBWIND		0x0300
+#define NBWMASK		0xF700
+
 /* Power Bus Common Queue Registers
  * All PBCQ and PBAIB registers are accessed via SCOM
  * NestBase = 4010C00 for PEC0
@@ -3810,16 +3817,13 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 
 	/*
 	 * Bit [0:7] XSL_DSNCTL[capiind]
-	 * Init_25 - CAPI Compare/Mask
+	 * Init_26 - CAPI Compare/Mask
 	 */
 	out_be64(p->regs + PHB_CAPI_CMPM,
-		 0x0200FE0000000000Ull | PHB_CAPI_CMPM_ENABLE);
+		 ((u64)CAPIIND << 48) |
+		 ((u64)CAPIMASK << 32) | PHB_CAPI_CMPM_ENABLE);
 
 	if (!(p->rev == PHB4_REV_NIMBUS_DD10)) {
-		/* Init_24 - ASN Compare/Mask */
-		out_be64(p->regs + PHB_PBL_ASN_CMPM,
-			 0x0400FF0000000000Ull | PHB_PBL_ASN_ENABLE);
-
 		/* PBCQ Tunnel Bar Register
 		 * Write Tunnel register to match PSL TNR register
 		 */
@@ -4141,7 +4145,10 @@ static void phb4_init_ioda3(struct phb4 *p)
 	/* See enable_capi_mode() */
 
 	/* Init_25 - ASN Compare/Mask */
-	/* See enable_capi_mode() */
+	if (p->rev != PHB4_REV_NIMBUS_DD10)
+		out_be64(p->regs + PHB_ASN_CMPM,
+			 ((u64)ASNIND << 48) |
+			 ((u64)ASNMASK << 32) | PHB_ASN_CMPM_ENABLE);
 
 	/* Init_26 - CAPI Compare/Mask */
 	/* See enable_capi_mode() */
@@ -4741,6 +4748,13 @@ static void phb4_add_properties(struct phb4 *p)
 
 	/* Indicate to Linux that CAPP timebase sync is supported */
 	dt_add_property_string(np, "ibm,capp-timebase-sync", NULL);
+
+	/* Tell Linux Compare/Mask indication values */
+	if (p->rev == PHB4_REV_NIMBUS_DD10)
+		dt_add_property_cells(np, "ibm,phb-indications", CAPIIND, 0, 0);
+	else
+		dt_add_property_cells(np, "ibm,phb-indications", CAPIIND,
+				      ASNIND, NBWIND);
 }
 
 static bool phb4_calculate_windows(struct phb4 *p)
diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index 2dc64fe5..829d9ecb 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -71,8 +71,8 @@
 #define PHB_PEST_BAR			0x1a8
 #define   PHB_PEST_BAR_ENABLE		PPC_BIT(0)
 #define   PHB_PEST_BASE_ADDRESS		PPC_BITMASK(8,51)
-#define PHB_PBL_ASN_CMPM		0x1C0
-#define   PHB_PBL_ASN_ENABLE		PPC_BIT(63)
+#define PHB_ASN_CMPM			0x1C0
+#define   PHB_ASN_CMPM_ENABLE		PPC_BIT(63)
 #define PHB_CAPI_CMPM			0x1C8
 #define   PHB_CAPI_CMPM_ENABLE		PPC_BIT(63)
 #define PHB_M64_UPPER_BITS		0x1f0
-- 
2.16.1