[Skiboot] [PATCH] ATTN: Enable flush instruction cache bit in HID register
stewart at linux.vnet.ibm.com
Tue Feb 13 19:29:19 AEDT 2018
Vasant Hegde <hegdevasant at linux.vnet.ibm.com> writes:
> In P9, we have to enable "flush the instruction cache" bit along with
> "attn instruction support" bit to trigger attention.
> Signed-off-by: Vasant Hegde <hegdevasant at linux.vnet.ibm.com>
> "flush the instruction cache" bit is disabled by default. Hence I
> think we don't have any side effect.
and since we only ever enable_attn() right before __trigger_attn(), then
we should be fine anyway :)
Merged to master as of 85f55e36bbd27fb9f75ba7cec912fd24490570ed
OPAL Architect, IBM.
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