[Skiboot] [PATCH] npu2: Disable TVT range check when in bypass mode

[Alistair Popple]

On POWER9 the GPUs need to be able to access the MMIO memory space. Therefore
the TVT range check needs to include the MMIO address space. As any possible
range check would cover all of memory anyway this patch just disables the TVT
range check all together when bypassing the TCE tables.

Signed-off-by: Alistair Popple <alistair at popple.id.au>
---
 hw/npu2.c | 39 +++++++--------------------------------
 1 file changed, 7 insertions(+), 32 deletions(-)

diff --git a/hw/npu2.c b/hw/npu2.c
index 1f7a1e0c..9e1e7b4b 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -879,11 +879,10 @@ static void npu2_hw_init(struct npu2 *p)
 static int64_t npu2_map_pe_dma_window_real(struct phb *phb,
 					   uint64_t pe_num,
 					   uint16_t window_id,
-					   uint64_t pci_start_addr,
-					   uint64_t pci_mem_size)
+					   uint64_t pci_start_addr __unused,
+					   uint64_t pci_mem_size __unused)
 {
 	struct npu2 *p = phb_to_npu2_nvlink(phb);
-	uint64_t end;
 	uint64_t tve;
 
 	/* Sanity check. Each PE has one corresponding TVE */
@@ -892,37 +891,13 @@ static int64_t npu2_map_pe_dma_window_real(struct phb *phb,
 		return OPAL_PARAMETER;
 
 	if (pci_mem_size) {
-		/* Enable */
-
-		end = pci_start_addr + pci_mem_size;
-
-		/* We have to be 16M aligned */
-		if ((pci_start_addr & 0x00ffffff) ||
-		    (pci_mem_size & 0x00ffffff))
-			return OPAL_PARAMETER;
-
-		/*
-		 * It *looks* like this is the max we can support (we need
-		 * to verify this. Also we are not checking for rollover,
-		 * but then we aren't trying too hard to protect ourselves
-		 * againt a completely broken OS.
-		 */
-		if (end > 0x0003ffffffffffffull)
-			return OPAL_PARAMETER;
-
-		/*
-		 * Put start address bits 49:24 into TVE[52:53]||[0:23]
-		 * and end address bits 49:24 into TVE[54:55]||[24:47]
-		 * and set TVE[51]
-		 */
-		tve  = (pci_start_addr << 16) & (0xffffffull << 40);
-		tve |= (pci_start_addr >> 38) & (3ull << 10);
-		tve |= (end >>  8) & (0xfffffful << 16);
-		tve |= (end >> 40) & (3ull << 8);
-		tve |= PPC_BIT(51);
+		/* GPUs need to be able to access the MMIO memory space as well.
+		 * On POWER9 this is above the top of ram so disable the TVT
+		 * range check allowing access to all memory addresses. */
+		tve = 0;
 	} else {
 		/* Disable */
-		tve = 0;
+		tve = PPC_BIT(51);
 	}
 
 	npu2_ioda_sel(p, NPU2_ATS_IODA_TBL_TVT, window_id, false);
-- 
2.11.0