[Skiboot] [PATCH 3/6] hw/npu2: Common NPU2 init routine between NVLink and OpenCAPI

[Reza Arbab]

On Fri, Aug 17, 2018 at 06:44:38PM +1000, Andrew Donnellan wrote:
>Replace probe_npu2() and probe_npu2_opencapi() with a new shared
>probe_npu2(). Refactor some of the common NPU setup code into shared code.
>
>No functional change. This patch does not implement support for using both
>types of devices simultaneously on the same NPU - we expect to add this
>sometime in the future.

Verified that with this patchset, everything still seems to work fine 
(on a 4-GPU Redbud, at least).

[snip]
>@@ -1403,64 +1372,56 @@ static void npu2_probe_phb(struct dt_node *dn)
> 	 *
> 	 * Obviously if the year is now 2020 that didn't happen and you
> 	 * should fix this :-) */
>-	xscom_write_mask(gcid, 0x5011000, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011030, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011060, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011090, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011200, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011230, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011260, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011290, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011400, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011430, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011460, PPC_BIT(58), PPC_BIT(58));
>-	xscom_write_mask(gcid, 0x5011490, PPC_BIT(58), PPC_BIT(58));
>-
>-	xscom_write_mask(gcid, 0x50110c0, PPC_BIT(53), PPC_BIT(53));
>-	xscom_write_mask(gcid, 0x50112c0, PPC_BIT(53), PPC_BIT(53));
>-	xscom_write_mask(gcid, 0x50114c0, PPC_BIT(53), PPC_BIT(53));
>-	xscom_write_mask(gcid, 0x50110f1, PPC_BIT(41), PPC_BIT(41));
>-	xscom_write_mask(gcid, 0x50112f1, PPC_BIT(41), PPC_BIT(41));
>-	xscom_write_mask(gcid, 0x50114f1, PPC_BIT(41), PPC_BIT(41));
>+	xscom_write_mask(npu->chip_id, 0x5011000, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011030, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011060, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011090, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011200, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011230, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011260, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011290, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011400, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011430, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011460, PPC_BIT(58), PPC_BIT(58));
>+	xscom_write_mask(npu->chip_id, 0x5011490, PPC_BIT(58), PPC_BIT(58));
>+
>+	xscom_write_mask(npu->chip_id, 0x50110c0, PPC_BIT(53), PPC_BIT(53));
>+	xscom_write_mask(npu->chip_id, 0x50112c0, PPC_BIT(53), PPC_BIT(53));
>+	xscom_write_mask(npu->chip_id, 0x50114c0, PPC_BIT(53), PPC_BIT(53));
>+	xscom_write_mask(npu->chip_id, 0x50110f1, PPC_BIT(41), PPC_BIT(41));
>+	xscom_write_mask(npu->chip_id, 0x50112f1, PPC_BIT(41), PPC_BIT(41));
>+	xscom_write_mask(npu->chip_id, 0x50114f1, PPC_BIT(41), PPC_BIT(41));
>
> 	val = NPU2_NTL_MISC_CFG2_BRICK_ENABLE |
> 	      NPU2_NTL_MISC_CFG2_NDL_TX_PARITY_ENA |
> 	      NPU2_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA |
> 	      NPU2_NTL_MISC_CFG2_RCV_CREDIT_OVERFLOW_ENA;
>-	xscom_write_mask(gcid, 0x5011110, val, val);
>-	xscom_write_mask(gcid, 0x5011130, val, val);
>-	xscom_write_mask(gcid, 0x5011310, val, val);
>-	xscom_write_mask(gcid, 0x5011330, val, val);
>-	xscom_write_mask(gcid, 0x5011510, val, val);
>-	xscom_write_mask(gcid, 0x5011530, val, val);
>+	xscom_write_mask(npu->chip_id, 0x5011110, val, val);
>+	xscom_write_mask(npu->chip_id, 0x5011130, val, val);
>+	xscom_write_mask(npu->chip_id, 0x5011310, val, val);
>+	xscom_write_mask(npu->chip_id, 0x5011330, val, val);
>+	xscom_write_mask(npu->chip_id, 0x5011510, val, val);
>+	xscom_write_mask(npu->chip_id, 0x5011530, val, val);
>
> 	val = PPC_BIT(6) | PPC_BIT(7) | PPC_BIT(11);
>-	xscom_write_mask(gcid, 0x5011009, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011039, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011069, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011099, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011209, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011239, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011269, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011299, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011409, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011439, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011469, val, PPC_BITMASK(6,11));
>-	xscom_write_mask(gcid, 0x5011499, val, PPC_BITMASK(6,11));
>-
>-	index = dt_prop_get_u32(dn, "ibm,npu-index");
>-	phb_index = dt_prop_get_u32(dn, "ibm,phb-index");
>-	links = dt_prop_get_u32(dn, "ibm,npu-links");
>-	prlog(PR_INFO, "NPU: Chip %d Found NPU2#%d (%d links) at %s\n",
>-	      gcid, index, links, path);
>-	free(path);
>-
>-	/* Retrieve scom base address */
>-	scom = dt_get_address(dn, 0, NULL);
>-	prlog(PR_INFO, "   SCOM Base:  %08x\n", scom);
>+	xscom_write_mask(npu->chip_id, 0x5011009, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011039, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011069, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011099, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011209, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011239, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011269, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011299, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011409, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011439, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011469, val, PPC_BITMASK(6,11));
>+	xscom_write_mask(npu->chip_id, 0x5011499, val, PPC_BITMASK(6,11));
>
> 	/* Reassign the BARs */
>-	assign_mmio_bars(gcid, scom, reg, mm_win);
>+	assign_mmio_bars(npu->chip_id, npu->xscom_base, reg, mm_win);
>+	npu->regs = (void *)reg[0];
>+	npu->mm_base = mm_win[0];
>+	npu->mm_size = mm_win[1];
>
> 	if (reg[0] && reg[1])
> 		prlog(PR_INFO, "   Global MMIO BAR:  %016llx (%lldMB)\n",

Once this settles, I can do a follow-up patch that creates a 
setup_device() in npu2.c like you have in npu2-opencapi.c, collapsing 
all these ugly hardcoded scom writes into a loop of per-device writes 
with properly named values.

Acked-by: Reza Arbab <arbab at linux.ibm.com>

-- 
Reza Arbab